Ok this is "done while thinking and reading" ..
Yes "how do I do" well not using the 5 monitors really but using multiple windows open on the same monitor
Ok this is so far "the idea" and about "why those chips and not others" the answer is "because those I have them around here I don't need to go out and buy anything else".
Yes I've seen there are various static rams 16 bits x something, but they normally come in SOJ package or such, I've done my own adapters xxx to DIP quite a few times ( photo etched home ) still "I have chips around, let's use those".
The idea is starting to get shape, I still have one of those XC9536 around I am going to use that.
As I said 'why those flipflops and not the latches' or such is because thanks to the CPLD I can still generate strobes/etc. for them unfortunately that CPLD is a bit small so the latches "has to stay out".
One thing the manual seems to point is that to drive the "mode register" directly via BCLR is a bit "risky", you shoulc conider PUP as well to avoid to put stuff on the bus while PUP is not yet ok.
Also somewhere they suggest to consider always CAS together with RAS to avoid another bus problem when responding to an ASPI.
In that thing I want to also attach that SPI uart I got, the practicality of that uart is "only 3 pins necessary", I have to study a bit about that story that the T11 seems to always do a READ cycle even when doing a WRITE cycle, this can have some implications.
Anyway so far "as rough idea" that's where I am at, but now I have to stop doing this and I have to finish to prepare myself some stuff for a trip tomorrow, however I am going to bring with me also all this ( the schematics ) to work on during nights
SoFarT11.tif
Ah yes as you say today 'most stuff' is getting 3.3v but not really all of it so there's still some stuff to choose with.
Actually "packaging" is now a bit more of a thingy, DIL and such is vanishing almost totally replaced by SMD technology.
[edit] - forgot to say, the 27C64 in reality are some 28C64 EEprom I have, same pinout, same as a 6264 ram as well.
The rams I actually have around a few chips ( took of from some old '386 boards i believe ) UM61M256K-15, they are 15 ns 32kx8 static ram "usual pinout".
The latches .. "those I have here" even if they are not transparent ones it should not matter, in this case I should use NOT ( RAS ) to clock them.
I have to study a little about generating properly the RAMOE ( hi and low ), I think for the ROM I could use /OE = ( /CAS OR /RAS ) if course when it falls within the decoded address range I am going to use for the ROM
The "Mode register" I'll do it directly via the CPLD so not to add another chip out, I think I can too use the same idea they used in that Atari thing, all the other bits that are not 0 are guaranteed to be pulled up at '1', the CPLD has 3 state buffers in it, I can just connect some lines to the DALxx I need.
The "SPI port" is my "usual trick of trade", I've done it already a few times but you'll see when I'll put the VHDL up as well.
I still have to properly check timings but at 10 Mhz I should absolutely have 0 problems with those components.
[edit2] - forgot to say, no pins assigned to the CPLD yet, in those cases "I let the compiler choose", I first synthesize and test ( simulate ) the stuff THEN I lock the pins, so the compiler can choose better what it likes for what and the cells it prefers as well, I then add the pins/functions in the schematics as last thing.