UPDATE #2:
Jumping C8 pin 3 to D5 pin 9 - Works
Jumping C8 pin 3 to D8 pin 10 - Works
Jumping C8 pin 3 to C1 pin 11 - Works
I am not sure I understand here. Did you mean you lifted C8 pin 3 out of the socket and connected it to the three pins mentioned in turn? It should actually not work, I would assume all signals are necessary.
Or did you leave it in the socket and connected it to the three pins in turn with an extra connection, bypassing the trace and it works? Wouldn't really understand either that all pins work.
As a further analysis:
C1 creates the "inverse" enable signal which is used when a character has bit 7 set in the screen memory. It's output is fed into the XOR made up of C2 (NAND pin1-3, pin4-6) and E2 (pin1-3) to generate the video bitstream out signal. It could explain the overall weaker clock pulse if it would pull the signal down, but not the specifically lower pulse when DIS.ON goes high.
D8 is another beast. D8 creates the vertical drive (pin11-13). But that is not "in sync" with line generation, so it is unlikely that this causes effects in sync with the raster line start (DIS.ON going up). It is also used to compare the video address with some value (most likely something around 32768+1000
and generate a signal that clears the JK-Flipflop at C7, which then clears the memory counters, thus going back to address 0. This part is also unlikely to interfere with something that is in sync with rasterlines. Yet this part may still pull the clock signal low in general.
But: D8 actually creates the reset pulse for the clock pulse coming from C8 pin3, our problem child. When C8 pin 3 goes high, D8 pin 8-10 synchronize this signal with the 8MHz clock, then it is fed directly into the reset pin for our C8 pin 3 signal. So..: the 8MHz clock is on one side almost directly fed into the reset pin C8 pin 13. On the other side it is fed through counter C9 (divided by 8) and used as clock signal for C8. If C9 has aged and shows a different delay than it used to, the phase difference between the clock and the reset at C8 pin 13 may have changed, resulting in a much shorter (and thus weaker - as it does not have enough time to rise to full strength) clock. This could be an explanation for the in general lower and weaker clock pulse on C8 pin 3. Unfortunately not for the specific extra-weak pulse when DIS.ON goes high.
The only one of the three receivers of the C8 pin 3 signal that has a connection to DIS.ON that could explain the weaker pulse when DIS.ON goes high is of course D5, which has DIS.ON as reset signal.
So, to summarize. There are two options:
1) It is a power-related problem. Then any of the three ICs D5, D8, C1 could pull the clock pulse low and would likely show similar symptoms on other inputs. Also the chip could show a different temperature signature (being colder or hotter than the others)
2) It is a timing-related problem. Then it would be C9, or maybe even D8 that has aged and changed its timing characteristics.
To identify what is going on:
1) My suggestion is: Check the three ICs D5, D8, C1 in terms of signal quality on their other inputs. If one of these ICs "pulls", the other inputs (not only the one we investigate from C8 pin 3) may also be pulled and show a low voltage (similar to C8 pin 3 compared between the working and the broken PET). Finding such an input would probably even more of a smoking gun. Also you may check the quality of the supply voltage of these chips and compare them with each other. Maybe also check if one of those gets hotter or colder than the others.
2) compare the signal quality (pulse width, timing relation to DIS.ON - note for the latter it may be difficult to see differences, as the timing difference would only be in around 10ns) of C9 pin 1 (8MHz clock, same as D8 pin 9), C9 pin 11 (1MHz clock, same as C8 pin 12) and D8 pin 8 (reset signal for our clock, same as C8 pin 13) between the working and the broken PET.
(Note no need to put it up all on pictures if you don't see differences, to avoid unecessary effort)
André
