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Need some help with interpreting octal code

no my 11 still has its lsi11 someone did upgrade it to 32k memory tough from 16k

the manual is from the unit that woulda been at ratan mine (leaf rapids, MB)
 
Ancient Book Review

Ancient Book Review

Ok, got my first pick of a decent PDP-11 book for you guys.

Code:
"[B]MACHINE AND ASSEMBLY LANGUAGE PROGRAMMING OF THE PDP-11[/B]" Second Edition - Arthur Gill

Prentice Hall
ISBN 0-13-541888-7
Hard cover 7x10
185 short pages plus Appendices and an Index.
The Pros:

This is targeted for programmers already experienced in high level languages, who may not have ever programmed in assembly or machine code before on any machine.


  • It includes a concise review of Data Types as pertain to the PDP-11
  • A very nice treatment of the instruction set, opcodes, syntax, addressing modes
  • It's very "practical" pointing out the customary PDP-11 novice mistakes often seen
  • Has example program segments with an opcode analysis and commentary


The Cons:

It's written by a Berkeley type guy... so it includes the customary "invented" abbreviations and notation that never caught on anywhere else.

Fortunately, it doesn't get in the way too much, and the result is still way above the other's I've reviewed for you so far.

Warning:

Be certain to get ONLY the Second Edition. The First apparently has a few errors that will doubtless drive the student NUTZ!

Summary:

I like it stylistically. I read through to chapter 6 in an hour. [not skimmed] It reads linearly like a novel, but has an index to help you later when you need to investigate specific questions.

It's not tiresome or boring to read. On the contrary - it contains many "human" hints and comments that make the topic quickly comfortable.

The main thing it offers is an appreciation of the "Opcode" architecture of the machine. This will have you writing and converting programs to code immediately.

I'll finish it later to be sure, but already I can recommend it based on what I've seen.
 
I agree. My copy arrived yesterday and I sat down and read the first six chapters before dinner. There is a character echo program to help with testing the baud rate to the teletype too.
There were a lot of typos but I had an erata supplement that caught many of them.

Its written for the 11/10.

FYI Yesterday I loaded a bootatrap loader type papertape ..

Bd
 
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Review of "MINICOMPUTER SYSTEMS..." Eckhouse & Morris

Review of "MINICOMPUTER SYSTEMS..." Eckhouse & Morris

Code:
    [B][SIZE=5]MINICOMPUTER SYSTEMS[/SIZE]
            ORGANIZATION, PROGRAMMING, AND APPLICATIONS (PDP-11)" - Second Edition[/B]

Richard H. Eckhouse, Jr.
L Robert Morris

Prentice-Hall
ISBN 0-13-583914-9
On the cover: Diagram of the "Antikythera Mechanism" [[URL="http://en.wikipedia.org/wiki/Antikythera_mechanism"]1[/URL]][[URL="http://www.antikythera-mechanism.gr/"]2[/URL]][[URL="http://www.antikythera-mechanism.com/"]3[/URL]] 
491 Pages including Appendices and Index
This book would have been very useful had it been known to me in my early PDP-11 career. Not for programming, but for it's appeal to me as an Architect of several operating systems.

It is a Computer System "Designer's" view of the PDP-11's instruction set with a general appreciation of the issues and decisions of it's implementation and use.

It delves into "Intermediate Level" topics such as data types, algorithms, linked lists, stacks, relocation, I/O, interrupts, reentrancy, recursion, and organization by examining use in example Realtime programs, including a "Modest" OS.

Examples frequently include opcode, but don't focus on it for the most part. It would be difficult to concieve of learning many of these techniques without having a MACRO-11 compiler to practice on. There is a brief examination of High Level Language vs Assembly, and another on debugging, but coverage is light and not advanced enough for my taste.

A more advanced section discusses PDP-11/60 "Microcode". This won't be interesting to everyone, but it provides an "internals view" of how this was accomplished which is hard to come by.

Overall - this book won't help you much on your PDP-11 fundamentals. It's definitely targeted at those with ambition to move beyond entry level assembly programing by providing a foundational understanding.

It could also be a supplemental resource as a reference book to those who might be interested in systems level topics, without the need to fully utilize them yet.

Readability - it doesn't really speak easily to anyone but us aliens who might already be familiar with what the authors are getting at. Novices should expect to have several other books open at the same time, the deeper they get into it's carefully "woven" structure. Even then, it might be a frustrating experience.

I can't say it's an RT-11 "Primmer", but I expect it could be a reasonable introduction into OS topics that would make a nice prep for an RT-11 specific book/course and a prerequisite if you want to examine the sources. Less so for UNIX or RSX, but nonetheless useful to get one "on the road".

I am afraid it won't be directly useful to get a novice up and coding for the PDP-11 in opcode. It does include a Console Switch register operation overview that might come in handy and a treatment on UNIBUS. Here and there there are other desirable details, but it's not really organized for this group.

Conclusion:

I like this book for my own reasons. I am not sure it will be immediately useful to others. It may be one of those purchases you appreciate better in a few years, if you stick with PDP-11 programming. It's cheap enough to buy on that basis, and take the chance.
 
Review of "The MiniComputer in the Laboratory" Cooper

Review of "The MiniComputer in the Laboratory" Cooper

Code:
[SIZE=5][B]The MiniComputer in the Laboratory[/B][/SIZE]
[B]            with examples using the PDP-11
[/B]
Author: James W. Cooper

Publisher: John Wiley & Sons
ISBN: 0 471 01883-X
309 pages plus bibliography, appendices and index - 368 total

Cut to the chase
- of the books I've reviewed so far, this has one of the most concise, complete opcode views of the PDP-11 I've encountered. Not for it's thoroughness in covering the instruction set, but for imparting to the reader the SPIRIT of the machine's layout.

In this way, it's architecture is not "lost in the details".

Separated into TWO major Parts, "PART I" contains 13 of the best written chapters introducing and describing the PDP-11 I've ever seen.

It begins with the customary review of preliminary information about DATA types and memory, but immediately separates itself by going into logical operations on data with concepts of AND, OR, XOR, Compliment and 2's Compliment math.

Chapters 3-6 cover the machine itself, and you will read them hoping you can memorize every word.

If there is a weakness to the work, it's that the MMU is mostly ignored. From what I can see, this treatment is purely for UNIBUS, "unmapped" machines.

I see this more as a strength however, since I don't encourage novices to get bogged down with these concepts until they are ready to graduate from INTERMEDIATE to ADVANCED level programmers. In my mind, this makes it nearly ideal for beginners, yet contains the necessary formative details often neglected elsewhere.

It is written to be very practical. Each section of information includes exercises to cement the concepts covered, in place. [Answers in the Appendix]

Also included in PART I are sections on Usage, Subroutines, Stacks, Interrupts, ODT, ODT-X, Loaders, Assemblers and host development systems [I.E. - PDP-10 and RT-11]

Part II contains sections on the LPS-11 [I/O subsystem] and example programs that will illustrate just how much one can do with the instruction set and assembly code in general. All examples are given in mnemonic source form, with commentary and analysis. Topics include FFT [Fourier Transform], data presentation, peak detection, and interpolation among them.

Conclusion:

Well, I've already said. This is a detailed treatment for the experienced "programmer", who only needs an into to PDP-11 topics and techniques. It's not boring to read, it's chock full of juicy details that answer questions directly - that one often finds chapters apart in other texts.

Yes, there are good appendices and other reference sections, but for me, "PART I" in it's entirety - is the real gem here.

A final note about LSI-11 and QBUS - These are not mentioned at all in this book. However, as in other DEC documentation, I consider this an asset. These were "Follow-On" PDP-11 families to the UNIBUS machines. As such, they built extra layers onto their UNIBUS Ancestor's fundamentals. To read a UNIBUS directed description, is to see the PDP-11 foundation in an unobstructed way. It is completely relevant to later machines and buses.
 
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Hey..just a quick update. I have been able to get my PDP 11/05 to print all the alpha characters to the teletype.

Rather than use an oscilloscope to adjust the baud rate I brought in my synthesizer. I set an echo pulse to 110 bbm and got the teletype to be in synch musically with the synthesizer. I compared with 220beats per minute, etc. I realize that you can't get away with this on a faster baud with compression, etc. but I do have rhythm, and I was able to use this technique to my surprise, effectively. For those of you making the adjustment to the pdp 11/05's M7260 processor card, it's a rather fine adjustment to get it exactly to 110 baud.
 
That's the most novel use of test equipment I've heard in quite some time.

Glad you got it sorted out. You're really off and running with this project from where you started.

Congrats Bill.
 
i duno if this would help but its outa my h11 software manuals
http://pointdouglas.com/SEBHC/H11/H11-software-ref-manual011.pdf

I found the full manual set at that link very interesting. [Thank You] Do you know where I could download the paper tape binaries mentioned in that documentation?
I.E. - PAL-11, LINK-11, ODT-11X, uODT BOOT, IOXAP, ABS LDR, FOCAL, BASIC, and so on?

Will someone be putting up all sections of the Operations Manual as well?
 
by this weekend i could have one or 2 up depending if i get the asr33 at the local hacker space going... also hows one make a binary of the tape?

operatrations manual was complted last night now to the next binder...........

the black ones are for the h89
5147199615_40a2d7b576_b.jpg


... like 4 trays of software and a zenith box full of software for the h11.......
scaled.php



4 copies of space wars
modicon
tital
asembly through put
life ??? duno what that is
dec-11-uabda pdp11 absolut loader 07/27/78
graps in basic
caves
tansistors ???? has some other rightig on it like error 5183
heath/dec -11-uabrlb-a-po C1975
880-33 odt-11
880-100 input/output
880-22 mem dump
mini text edidit
modifyed text editor in basic apr 83
coss-4 code 2470 532-9e 1978-04-27
caners pull qoter june 83 ?? hand riten hard to read
ibm type test a-z 0-9
abs loader
1972 payroll data
pay roll
880-23
880-99 basic
880-82 focal eis/fis 4k
880-83 focal eis/fis 8k
880-53 pal 11-&
880-55 editor
880-102 link 11s
mystry 5
 
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Thanks for those.

I've had a look at the Operations Manuals and have a question already...

The Table of Contents shows a "Schematic (fold in)" coming after the "Semiconductor Identification Charts" (5-23 to 5-40) as the final thing before "Section 6".

Are these present in your copy?

...I don't see them in any of the PDFs.
 
Well, those are exactly the kind of design I was hoping they would be. So far, drawings include assembly, parts placement and artwork. I'm still hoping there will be an actual Schematic, although with the XRAY view you posted, one could be re-created.

I encourage you to gather those and re-shoot them in high resolution with a graphics camera as complete sheets. Obviously, they are going to be too large for the bed of most scanners.

You might ask: "Why are these so important?"

These designs are unusual for QBUS compatible boards. They do not appear to employ the usual DEC standard ICs in the QBUS interface. Rather they use standard LS logic for this function.

Therefore, this design offers an important example of how the QBUS specification may be accomplished using hardware available today.

Your choice to begin with the Serial Card is fortuitous, in that it has to contain logic to deal with the interrupt chain, one of the more difficult to accomplish pieces of puzzle.

Also, HEATH's documentation is perhaps the best ever. The XRAY sheet, for example, will greatly assist anyone in troubleshooting one of these boards - way beyond the customary documentation, even DEC's originals - which themselves are excellent for the industry.

In other words, what you have is a treasure and well worth the time you are spending.

I thank you for investing the effort to save and share these. Your work here may be enabling far more than you could imagine. It could provide the opportunity for hobbyists to implement replacement QBUS designs or repair parts for DEC originals.
 
Well, those are exactly the kind of design I was hoping they would be. So far, drawings include assembly, parts placement and artwork. I'm still hoping there will be an actual Schematic, although with the XRAY view you posted, one could be re-created.

I have finally gotten around to doing this, sort of. What I have is the board re-drawn in Eagle CAD, and
the ERC & DRC errors and warnings cleaned up. The schematic is still mostly a pile of chips, gates, and
whatnot, with each pin labelled with a signal name.

You might ask: "Why are these so important?"

These designs are unusual for QBUS compatible boards. They do not appear to employ the usual DEC standard ICs in the QBUS interface. Rather they use standard LS logic for this function.

Therefore, this design offers an important example of how the QBUS specification may be accomplished using hardware available today.

I can tell you that the bus lines are received with 74LS240, and written (just the bottom 8 bits) with 74S240.
A single 7438 drives OC outputs for BIAKO\, BIRQ4\, and BDAL15\ (that last, I dunno why). I'm pretty sure
that in no way meets qbus spec's. I haven't done the work to figure out the restrictions on qbus that would
be needed to be compatible with this board, but I suspect they get away with it because it is a single small
backplane, all powered up together, etc.

Your choice to begin with the Serial Card is fortuitous, in that it has to contain logic to deal with the interrupt chain, one of the more difficult to accomplish pieces of puzzle.

Hmm. I don't pretend to know what's going on there, but for BIRQ4\, I see a couple sections of an LS10
(3-input NAND) feeding a 2-input NAND, which is then inverted by an OC 7438 NAND with it's inputs tied
together. One of the 3-input gates has inputs from one pair of status flops and a clocking signal. The other
has the other pair of status flops and a different clocking signal.

For IAKO, it seems to be IAKI ANDed with outputs from a couple of the status flops.

Is there something else I should be looking at?

Vince
 
Hi Vince... yes, those are just the kind of details of interest.

A 7438 with open-collector outputs can sink 48ma when pulling an output low. Applying those directly to bus lines implies wire-or treatment in some cases, and daisy chained signals in others.

Use on BDAL15 was probably to implement a bit in a status register which contained no other high order bits.

The general description of IAKs and BIRQs also fits with the daisy chain processing of interrupt acknowledge on the bus using clocked logic.

You can dig DEC manuals for some time and not find clear examples of these in discreet logic.
 
Hi Vince... yes, those are just the kind of details of interest.

A 7438 with open-collector outputs can sink 48ma when pulling an output low. Applying those directly to bus lines implies wire-or treatment in some cases, and daisy chained signals in others.

Yes, though a proper 8881 or 8641 can sink 70ma.

Use on BDAL15 was probably to implement a bit in a status register which contained no other high order bits.

Yes, that is it exactly. It implements the "error" bit in RBUF, and the "DSR" bit in RCSR. Interestingly, the
more specific error bits in the high half of RBUF are not implemented.

The general description of IAKs and BIRQs also fits with the daisy chain processing of interrupt acknowledge on the bus using clocked logic.

I've figured out that BIAKO\ is derived from BIAKI\, and neither the input or output interrupt latches being set.

You can dig DEC manuals for some time and not find clear examples of these in discreet logic.

Well, I'm not sure how clear they are here, though I've made some progress figuring out the schematic.
I've got the stuff correctly labelled (rather than the default N$nnn generated signal names) for a couple
of levels in from both the bus and the terminal, now. I've been able to identify the interrupt enable and
interrupt request latches, buffers and level converters, and the baud rate generator and UART. I've got
part of the bus output mux figured out, but my understanding much of the logic that controls it is still hazy;
for instance, I don't yet get how it decides when to route the interrupt vector onto the bus. In fact, only
about half the stuff being constructed with individual gates is really clear to me at this point. Nonetheless,
I am now at least able to see roughly how the thing works.

There are some other strange things, like how the FET is being used, that I don't get at all, too.

Vince
 
Eagle-CAD drawings for H11-5

Eagle-CAD drawings for H11-5

I have uploaded a set of H11-5 drawings in Eagle-CAD format to
http://www.so-much-stuff.com/pdp8/cadlib.html.

You can scroll the "boards and schematics" region down to the H11-5, and
download a .zip of the Eagle files. If you need the PDF, you can also get
those by changing the URL which that sends you to from
http://www.so-much-stuff.com/pdp8/cad/projects/H11-5/h11-5.zip
to
http://www.so-much-stuff.com/pdp8/cad/projects/H11-5/h11-5pdf.zip

You can also get to much of my other work, such as it is, from the cadlib page.

Vince
 
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