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Forthcoming XT-IDE Board - Cast Your Vote

Forthcoming XT-IDE Board - Cast Your Vote

  • As original XT-IDE, with a 40-pin header only

    Votes: 4 10.5%
  • With a 44-pin header and board space to mount a 2.5" IDE HDD (i.e. a hard-card)

    Votes: 7 18.4%
  • With an optional Compact Flash socket (as master or slave) and a 40-pin header

    Votes: 26 68.4%
  • With a Compact Flash socket only

    Votes: 1 2.6%

  • Total voters
    38
  • Poll closed .
I'm trying to get a Rev.P1 of the ISA version out to fab at the end of the week. Will take 2-3 weeks from that point to get them to the first builders. I'll be honest, Rev.P1 of this ISA version will likely only have a .1" 40 pin header and possibly a 4 pin .1" power header. It will also have no current code support in XT-IDE Universal BIOS as it is all memory mapped with a strange layout.

It is also a CPLD version. I'm changing the header to work with a standard ByteBlaster II parallel port cable (eBay $16 shipped), but it will require programming the CPLD unless someone is willing to program kits for folks.
 
I thought the V2 was getting to be a little too involved for what it was.

Do people want a "build it yourself" board or a "built by someone else" board? If the answer is "build it myself", then the V1 XTIDE (with perhaps a couple of very small changes) is still the best bet.

If nobody cares for the DIY experience, I think its a shame, but it answers the question for this and other future projects.

I think that there is still a market for the v1 XT-IDE bare board, honestly, just because it's a relatively simple build with no special equipment. It's just to someone to take the publicly-available files, send them off to a PCB manufacturer, and get them made. That said, there's a cost involved, and that someone would have to be willing to put the money up-front as Andrew and Hargle have done, or there would have to be a "collection" made, and if the "target" isn't reached, then everyone is refunded money. The latter is safer for the main person doing the work, obviously, but also is the slowest method to get the equipment into the hands of end-users.

And then there are the people who aren't capable or willing to build there own - and I was one. I ordered a pre-built one from Hargle to ensure that I had a working board while I learned to solder on the other bare boards that I ordered from Andrew.

And then there is the consideration of the CPLD boards that are being developed. I think that there is room for both, because the CPLD boards are obviously expandable, although it's a valid point that if the market is saturated with too many similar products, then we run the risk of people losing money on their community venture due to the limited target audience, and that's not good for the community either.

Decisions, decisions....
 
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CF is 21st century? From my understanding, they're on the way out, being replaced by higher-capacity, cheaper, and ever-faster SDHC cards, whether full-size or micro.
CF is still VERY popular with industrial, and professional users, its only bee supplanted in "cheap" retail crap, I have yet to meet an SD card as fast or as high capacity as CF cards, and the only "cheap" SD cards are slow as heck, almost useless for hard drive replacements. Also since CF is at its heart IDE, its like $0.03 to add a CF socket to a board like this, vs the extra support chips, resistors, and capacitors, and the like that must be added to drive an SD card (granted if this is CPLD driven there's probably enough "spare" IO lines on it to also drive a SD card, but there would still be extra resistors and capacitors and the like, costs would be higher to implement SD).

I say long live CF and I hope a CF slot makes its way into this project, and I will be all over one.
 
CF is still VERY popular with industrial, and professional users, its only bee supplanted in "cheap" retail crap, I have yet to meet an SD card as fast or as high capacity as CF cards, and the only "cheap" SD cards are slow as heck, almost useless for hard drive replacements. Also since CF is at its heart IDE, its like $0.03 to add a CF socket to a board like this, vs the extra support chips, resistors, and capacitors, and the like that must be added to drive an SD card (granted if this is CPLD driven there's probably enough "spare" IO lines on it to also drive a SD card, but there would still be extra resistors and capacitors and the like, costs would be higher to implement SD).

I say long live CF and I hope a CF slot makes its way into this project, and I will be all over one.
I didn't say that the tech wasn't good or that I didn't prefer them, but when the latest DSLR camera options from Nikon, Canon, etc utilize SDHC rather than CF, there's a reason... whether marketing, pricing, or both. CF is superior... but so was Beta. SDHC is still growing, is getting ever faster, and is certainly cheaper. For better or for worse. That said, by the time CF isn't available, and our CF cards give out, our hardware will be closer to 50 years than the 30 years, so... the point's moot.

Also, so far as hard drive replacement... even the slowest SD is faster than the limits of the hardware interfaces that we're dealing with on XT-class machines. Meh.
 
Anyone know more about how I can get more involved with the XT-IDE discussions? Both hardware for Mk.II going forward and xtuniversalbios on Google code (I can't figure out how to join the project!)

Anyone who wants to commit to XTIDE Universal BIOS should send me a private message or email.
 
Increasingly, the world is moving toward serial bus architecture. SATA, USB, PCIe, HT, FC. As silicon speeds go up, the need for the complexity and real-estate of parallel interfaces is going down. Heck, modern SSDs use SATA. As a matter of fact, CF, to the best of my knowledge, is the last physical currently-manufactured manifestation of the parallel IDE bus.

SD is getting faster. It'll catch up.
 
I'm not sure CF has a definable shelf-life just yet... all of canon's single-digit DSLR bodies use them for example. But I personally have nothing against SD either, I use one with an original XT/IDE in a 5155 as it happens - which works just fine!
 
Quick update. I'm sad to see that Andrew doesn't have much time to work on his successor board. There is certainly a lot of merit in a self-bootstrapping design. Any PLD design has a big draw-back in that respect. I'm also glad to see DP doing their thing too as their design addresses several things not on my radar. So not to cause any confusion with the XT-IDE name, I'm simply referring to my board as the JR-IDE/ISA since it is a cut down of the board that is currently in testing over on the JR forums.

I have to unexpectedly head to Texas for the weekend for work so I can't get the first ISA prototypes (and 2nd JR prototypes) ordered this weekend. However the ISA version is completely routed and coded. Since I'll have a few more days till the next group panel buy on Dorkbot, there's time for a little design review! The schematic, board files, and BOM are available here. When I stop in at work tomorrow, I'll add the PLD code to that file list.

This is a less feature rich board than Andrew or Ian have in mind. The DP board is coming and will include all my features plus others and hopefully some lessons learned too. So if you don't like what you see, hang on for their version. It will be better and they already have an ISA variant in live-test. The timeline for this one is going to be a couple months out for mass available kits anyway. So don't send me any IMs asking for boards. The existing BIOS principles have offered to assist with coding differences in exchange for early copper. Personally I think they sold themselves short as I was about to put 'other favors' on the table too. Couple other notes:

- Single 40 pin .1" IDE header. No 44 pin board mount or CF.
- 4 pin .1" aux power header
- Memory mapped I/O (>300 KB/s @ 4.77 MHz)
- Optional one wait state operation
- Co-layed out for 28-pin JEDEC ROM up to 32 KB or 32-pin 39SF0x0 flash part up to 512 KB with extra capacity going to a ROM disk. Though I'm tempted to cut the 28-pin socket pads.
- 16 KB dip-switch mapped dedicated ROM BIOS and register window
- 8 KB dynamically mapped panning flash access window.
- In-circuit programming via relatively cheap eBay parallel cable & free software.

It's pretty no frills. However if there is enough interest from people once a final version is ready, I'll front a batch buy of PCBs, limited parts kits, and programming cables and you can buy ala cart. Even if you don't think you have anything to contribute to reviewing the board and (tomorrow) code, don't sell your self short. An extra pair of eyes following the logic path never hurts and always reduces bugs. And I'd thank you!

-Alan
 
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Saying it's no-frills is WAY short of the mark! Memory-mapped IO, full CPLD implementation, ROM-disk, ZWS... it's a great looking bit of work :)

A couple of comments:

- IDE_CSEL looks to only be low - this, if I've understood the specs correctly, will prevent operation with ATA-1 or 2 drives. Not of course that that is likely to be a huge concern.

- It looks to me that the PD on DD7 should be 10K (47K on the schematic)?

Here's the simple test program I've been using with the DP prototype - provides performance and pattern tests via the file system, so should work on anything (I had problems with eg Nortons as I guess it's coded at a very low-level to operate directly with MFM/RLL drives). It's simple (and I'd very much welcome any comments on it) but it has picked up some issues so seems to be effective.

HTH!
 
- IDE_CSEL looks to only be low - this, if I've understood the specs correctly, will prevent operation with ATA-1 or 2 drives. Not of course that that is likely to be a huge concern.

Ok, what does the ATA-1/2 spec say? 4 requires the device have an internal pull up. Thus I either leave it floating on the host or ground it.


- It looks to me that the PD on DD7 should be 10K (47K on the schematic)?
I wanted to weaken the pull down to give a bit more margin for old crusty drives. 10K is a spec minimum. 47K should be fine. Since it's a part value, it can be changed on the fly if needed.
 
Ok, what does the ATA-1/2 spec say? 4 requires the device have an internal pull up. Thus I either leave it floating on the host or ground it.

My mistake on this, sorry - I was reading "6.3.15 SPSYNC:CSEL (Spindle synchronization/cable select) (Optional)
This signal shall have a 10K ohm pull-up resistor.", failing to notice this is talking about the DRIVE. So this being the case, the option to select CSEL as Vcc or Gnd via a 10k resistor appears to be wrong, and should be changed in the DP design. I'll modify the prototype and check.
 
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Hi Alan, sorry for the idiot question but I'd really like to get a better understanding of the CPLD side. Is there some application I can download to view the effective schematic the CPLD code generates?
 
the option to select CSEL as Vcc or Gnd via a 10k resistor appears to be wrong, and should be changed in the DP design. I'll modify the prototype and check.

Just to confirm this. I tested the (DP) XT/IDE with an 80-pin cable and two drives connected, both in CSEL mode, and neither were detected (both presumably configured as slave). After re-routing IDE pin 28 directly to ground, both drives were correctly detected and the system booted from the primary.
 
Hi Alan, sorry for the idiot question but I'd really like to get a better understanding of the CPLD side. Is there some application I can download to view the effective schematic the CPLD code generates?

It's written in CUPL and synthesized with WinCUPL - which is an absolute abomination. It's not a mature product and the language itself is dead. The choice to use it was driven by the part choice. The Atmel PLDs are the only currently available 5V through hole parts that aren't insanely expensive. And Atmel is also behind curve in that they do not give away Mentor or Synopsis driven synthesis software for free for low end devices (probably because Atmel doesn't make any high end). They have a WinCUPL programmers reference floating around. That's the best guide. But the product doesn't give you a floor plan view, schematic view, cell view, timing level analysis, propagation path reports, etc, etc, etc... you know, everything that is actually useful from Quartus, Diamond, and ISE Webpack. It does however give you an abundant amount of crash dialog boxes.

But I still feel the part is a better fit than most to the point it makes dealing with it worth it. However my opinion has softened lately.

FYI, I did find an obvious error in the source while I was reading it on the plane here. I'll leave it as an exercise to find.
 
Many thanks for the detailed info! Hopefully there are some skilled others looking at it... chance of me finding whatever the problem is will be probably about zero :)
 
FYI, I did find an obvious error in the source while I was reading it on the plane here. I'll leave it as an exercise to find.

Alan, I'm just starting out with this stuff, but is the error here by chance,

OPTION_WIN = A19 & A18 & !A17 & !(A16 $ CFG1) & !(A15 $ CFG2) & !(A14 $ CFG3);
 
Nope. That is the address decoding for the option window (ROM + regs) in main memory space. It can be located in 16KB steps from C0000 to DC000. A19 and A18 must be equal to 1, A17 must be 0, A16 must be equal to CFG1, A15 = CFG2, A14 = CFG3. The three CFG signals come in from the dip switches. It basically performs the same function as a '688 comparitor with A19 through A14 on one side and either dip switches or up/down straps on the other. OPTION_WIN is further qualified with other signals down the line to produce all the output strobes and to gate off other outputs.

The board order will be going out Friday.
 
Just an update, the order went out today for Rev.P1 of my ISA card. Will take about 2 weeks to fulfill and another to get them into the hands of some BIOS people for testing.

I'm not sure what's happened on the DP design. The forums over there have been pretty dead.
 
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