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8-Bit IDE Controller

The current requirements shall not exceed 75 mA at 3.3V and 100 mA at 5V." Also, Vih on the I/Os is minimum 2.4V when VCC is 3.3V and 4V when VCC is 5V.'.

The CF spec isn't clear on that at all. If you read the note, it refers to providing a high voltage of 90% of min Vcc for 5V signaling. What I'm not clear about is why that doesn't apply to 3.3V signaling? It refers to another specification that I cannot find. But that's a spec'd limit. Most 5V signaling devices are LVTTL devices and do not require a 4V+ level to register a one.
 
I'll look in to this more as it seems to be something that we need to get right. If I'm reading it correctly, it actually looks that the levels should be TTL for true IDE mode.
 
I think someone breaking the rule... :(

Check it out guys...

hxxp://www.ebay.com/itm/XT-IDE-ISA-HDD-CONTROLLER-CONNECT-MODERN-IDE-DRIVES-XT-MACHINES-8088-80286-/320765191316?pt=UK_VintageComputing_RL&hash=item4aaf186494

CMIIWR
 
What rule?

It doesn't matter if someone wants to resell something on eBay or not. This isn't a private club--anyone can join.

If someone wants to build any of the devices that have been rolled out here and sell them, what rule would be broken?
 
Perhaps I should fix up my non-working board, looking at the price! (towards building the next design I mean)
 
If anyone has a spare XT-IDE they might part with (in the US, preferably assembled & tested) I'd sure like to hear from you.
 
Hi
I continue to get requests for the original XT-IDE board but have none of the PCBs left. I thought the project (XT-IDE V1) was overcome by events since there are replacement projects underway such as the XT-IDE V2 (since shelved) and the CPLD XT-IDE project.

What is the status of the CPLD XT-IDE replacement project? Are you going to come out with a PCB? To be honest, I am not following the status all that closely. I think there is some work happening at Dangerous Prototypes and/or Mike Brutman's forum.

Is there a plan to release a new PCB? If so, when do you (whomever is leading the project) plan to release it? I don't want to push but I'd like to give builders who ask a reasonable answer on the way ahead.

Thanks and have a nice day!

Andrew Lynch
 
As far as I can tell the DP effort is dead. There have been no new posts over there in a while. I stopped contributing when Ian rolled back the design changes and didn't want to route the signals that would at least allow for memory mapped operation in the future. I'd still like to see that effort succeed going forward.

JR-IDE boards (both side car and ISA versions) are in the hands or on their way to the first builders. That includes hargle and aiotait who both have been busy with other things lately. The P1 ISA hardware and P2 Jr hardware has been proven out at a low level. The code isn't a big deal to write. Brutman is workin on that as well from the PCjr side.

However ideally I'd like to swap the PLD from an Atmel to Xilinx due to recent increases in cost/decreases in availabily. That won't affect software compatibility but may delay a group buy till a P2 spin. But once there is BIOS support, nothing would be stopping someone from sending the currend board files through (eg) DorkBot PDX for a 3 board order and builing up a board before the group buy is ready to happen. People can do that now if they'd like to early adopt; it's an open project. There is the down side of needing to purchase or build a Altera Byteblaster cable where as in a group buy, the PLDs would be individually shipped pre-programmed (cables ar $16 on eBay including shipping).

I personnally haven't had time to get a support site up or there would be more information to redily share. My appologies on that.
 
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While while I'm not actively hitting my head on the wall with it, the PCjr BIOS will be done sooner than later. (I plan on attacking it this week.) The changes will be easy enough for somebody to port back to the standard BIOS for use in an PC or XT.

(The memory mapping approach is really elegant ...)
 
Hi,
Is the JR-IDE a generic ISA board that anyone with an XT (or clone) can use or is it specific to the PCjr?

Thanks and have a nice day!

Andrew Lynch
 
Hi Andrew, Ian (at DP) has produced a second spin of a 'hybrid' CPLD design (where the data bus is still fed with discrete 74xxx logic) of which I'm planning to make up a few for distribution amongst members here in the next few weeks. It's just a partial CPLD port of you excellent original design.

For a full CPLD build, Alan's JR-IDE port design has progressed faster than the DP variety. Stumbling blocks have been Compact Flash socket, since unless varients with a high enough stand-off can be sourced the board size will be bigger than what is economically feasible, and secondly replacing the 27Cxx series EEPROM with something more cost effective and widely available, which I believe Alan's design is trialling some other options.

Later BIOS wise I submitted some bugs a few weeks back, but haven't had chance to look at that since.

So basically, WIP at the moment :)
 
The ISA card is generic. Will work in any PC/XT clone. It is the IDE & ROM portion of the JR side car board lifted up and put on a 8-bit ISA form-factor card.

The PLD could actually be eliminated if someone were interested in turning it back into a 74xx series project. A PLD was a logical (and in hindsight a correct) choice for rapid prototyping memory mappings. There were a number of code changes to address unforeseen problems and oversights that would have required many respins before hardening the design in fixed logic. Many modern ASICs and full systems are developed in this way using reconfigurable logic as a rapid prototyping tool.

I don't have a real 4.77 MHz bus clone nearby to test with atm, however some preliminary raw benchmarks on the JR seems to indicate 300 KB/s or more is possible using a single rep movsw to transfer in a sector. The only changes needed to the existing 74xx IDE designs is the carving out of an area at the top of ROM space for a 512 byte sector transfer window, a normal IDE 2x8 byte wide register area, and some additional combinatorial changes for latch enables and IDE address generation. The final PLD code can be used as a logical reference for anyone wanting to attempt it.

Unfortunately there is no current estimate on software as everyone is heavily interrupted atm including myself. But as soon as new mile-stones are reached, I'll post them here. I think all those involved with the project atm are intent on unifying software support (at least with the ISA version) with existing XT-IDE BIOS code. There is a board somewhere over the Atlantic for Tomi (Universal BIOS maintainer) to test with.
 
Hi
Any estimate when you are going to release a PCB? Are you planning on offering it to the public?

Thanks!

Andrew Lynch
 
In case anyone is desperate for a board, the Dangerous Protypes v1b board is available at no or minimal cost, five left apparently: v1b board
 
Here's a rendering of the card:

jride_isa_render.jpg

Here's a photo of P1: (ignore the vaporized trace on the left side!)

IMG_0076.jpg

The current pending change list includes:

- Change main CPLD from Atmel ATF1508ASL to Xilinx XC9572 and reassign pins
- Route IOW & IOR to extra pins on XC9572
- Eliminate configurable cable select / Make SW1-4 a ROM enable/disable select / Expand RN1 to 4 pullups to match
- Route +5V to through 1x2 .100" jumper to key pin (20) of IDE header for flash modules
- Plate through and unmask around screw holes for back-plate.
- Hard gold on fingers
- Update silkscreen with final URL
 
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All looking absolutely great - as ever.

With the addition of an optional VRM, it would be able to take an XC9572XL as well.
 
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