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Wanted: bus correction kit for AT&T 6300 (Olivetti M24)

I'll have a look at your circuit when I get a chance. In the meantime, here are the relevant files for a 22V10. I let the assembler auto-assign the pins (best to do on the 22V10, as outputs are different. A7 selects between the old and new mappings, just as in the old one.
 

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I'm impressed!

I'm impressed!

Wow... Chuck(G) and keepiru, let me just say I'm really impressed with your detective work so far! It seems that reverse engineering such a seemingly simple piece of kit is harder that it at first appeared... I'm afraid this stuff is way over my head with my current knowledge of electronics engineering... I switched majors from technical computer science to information technology back in my college years... If only I had taken the effort of finishing the former... I envy you wizards. :( Anyway, it's exciting to see how you are getting closer and closer to reproducing this upgrade kit. I somehow feel bad about leaving out the copyright notice. Do you think it would make sense to try to contact this Rick Fletcher person, to ask him if it's okay? I mean it's not like he's making any money off of this anymore. He might even be flattered to see some renewed interest in one of his old creations... But back to the two of you: thank you for putting so much serious effort in to this! I know you consider it a fun hobby as well, but still... :)
 
Chuck,
It looks like one of your equations has 16 product terms. That is an impressive use of a PAL.

Heh. I had to tweak things a bit--the first pass gave me 21 terms... :shock:

I could do just the modified bus correction scheme with 9 terms, but that's 1 too many for a 16V8, so the next logical try was a 22V10 and it turned out that I could do the old and new (jumperable) there.

Ain't programmable logic fun?

@digger

If you can find Rick Fletcher, I'm sure he'd get a kick out of hearing from you. Who knows? He might still have some unused stock left in his attic. There's no bigger kick than to be contacted because you left behind an Easter egg.
 
@Chuck(G): How hard is it to assign the pins manually? The random order is going to make the board look like a plate of spaghetti.

@digger: Chuck did the hard bits, dumping the ROM and probing the board, and coming up with a PAL program. It's pretty easy for me to design a new board when I know exactly what to make. :)

Pulling the copyright notice is just a practical matter. Including it in the PAL would be difficult. I do plan to give a shout out to him on the silkscreen on the boards. I'd love to get his blessing beforehand if we can track him down. I spent a while digging, but I can't find him.



The wizardry isn't so arcane once you know what's going on. Here, have some free knowledge:

The original 82S123 and the replacement 82S147 are parallel PROMs. The 82S123 is a 32x8: 32 memory locations, 8 bits each, AKA "256 bit". The address lines are A0 through A4 - 5 lines, thus giving us 2^5 = 32 addresses. You set each of those pins high or low, the chip looks up that memory location, and outputs the 8 bits on O1 through O8.

The 82S147 is a 512x8 (4kbit). The bus correction kit connects A0 through A4 into the same locations as the original chip. If we hardwired A5-A9 to ground and burned the original 32 bytes to the first 32 cells in the new chip it would work exactly the same. Instead it connects A5 and A6 to something on the 16-bit AT&T bus. I don't have a pinout so I have no idea what it is. But we now have 7 bits (128 memory locations) that are looked up to generate the 8 outputs. Since A7 is hardwired to ground, we have [128 bytes data] [128 bytes inaccessible] [128 bytes data] [128 bytes inaccessible] - the inaccessible parts are the text sections. A8 is connected to the jumper so you can manually choose the first or second 128 bytes of data.

Chuck thinks the purpose is to emulate some simple logic gates, and I think he's right. Basically if you have a small number of inputs into your logic network (Like 5-7, as we have here), and a small number of outputs (8 or fewer), you can just precompute all the outputs and burn them to a ROM. It's a neat hack.

The 82S147 is a "Bipolar" chip. that means "Bipolar junction transistors", used in Transistor-Transistor Logic == TTL. It's not very efficient with power, but it's quite fast for its era. In this case it's 45ns - set your inputs and in 45ns or less the outputs will be ready. That's about 22MHz, but there's a little more lag while it charges up the bus lines and the gates on any other chips, and we MUST be ready before the next clock. Still, it's plenty fast for an 8MHz bus.

Our replacement needs to be equally fast. EEPROM is based on CMOS, which came along later and is tremendously more efficient, but quite a bit slower. Of course, everything gets faster with time, so EEPROMs were getting faster... But lately parallel ROMs are considered obsolete and everything is going serial. Parallel EEPROM was just starting to get into the speed range that we need, but now it's being discontinued. Unfortunately the really fast stuff is already gone, probably because it was never in widespread use.

The other requirement is signal levels. CMOS == "Complimentary Metal Oxide Semiconductors". Complimentary means they use high-low pairs of transistors which greatly reduces leakage. The Metal Oxide Semiconductor part means field-effect transistors - MOSFETs, notice the MOS. The Field Effect part means the Metal Oxide insulates the transistor gates from the Semiconductor junction. Instead of constantly flowing current through the gate, it just charges up and the presence of the electrical field switches the transistor. That's great for power consumption, but it also means the gates require relatively high voltages to generate the field.

For a High level, TTL outputs guarantee 2.6V output, and require 2.0V (and high current compared to MOS) input; the difference gives you some noise margin. Early CMOS is about 3.8V in and out. While the open-circuit voltage is high enough, early CMOS didn't guarantee enough current to reliably drive TTL inputs (in practice it usually works). The hard part is the TTL outputs were hopelessly undervolting the CMOS inputs. In the 90s CMOS improved a lot, and practically all new chips are now specified to be compatible with TTL levels. Thus far all the replacement chips I've looked at are TTL compatible, but we still have to check.

So! What do we use to replace the chip?

EEPROM (easily reprogrammable) was my first thought, but Chuck's right: all the parallel EEPROMs 45ns or faster are gone.

PROM (cheap, but you only get to program them once) is still available. Atmel makes a 45ns chip that will work.

Flash (huge sizes for cheap!) is also available. Atmel has a 1Mbit 45ns chip that will work.

Chuck suggests the PAL / GAL. A PAL is a programmable logic array on a chip, which is exactly what the 82S123 was emulating! So we've come full circle. We just program the gates in the PAL to give the same combination of outputs given a set of inputs. It gives the same result as the ROMs, but it's really fast, around 3-5ns. I don't know how it works internally, but I'd guess it loads the flash into configuration registers on powerup.

Which is best? To me the flash looks easiest, but that's just because I'm familiar with them and I've never used a PAL. I think Chuk has done a lot more of this than I have so I'm deferring to his opinion, and since he's able to compile the program for the PAL it's no imposition on me either way.

So now you know, and knowing is dangerous. :)
 
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@Chuck(G): How hard is it to assign the pins manually? The random order is going to make the board look like a plate of spaghetti.

Within limits. The 22V10 is a bit peculiar in that 'middle" outputs can accommodate more terms than do the "edge" pins. Give me a proposed rearrangement and I'll see how close I can come. Just remember that left-hand (pins 1-11) pins are outputs and most of the right-hand pins (13-23) are outputs.
 
I don't understand the 9. The old chip only has 8 outs. Do you meant the bank select jumper? That's an input and shouldn't matter.

Anyway, proposed solution:
conv2.jpg

For the 82S147 signals ( O1..O8 ) this uses 10V22 output pins ( O0..O9 ) as follows:

Optimal:
8, 7, 6, 5, 4, 3, 2, 1

Preferred alternates:
Shift up or down:
9, 8, 7, 6, 5, 4, 3, 2
7, 6, 5, 4, 3, 2, 1, 0

Middle splits:
9, 7, 6, 5, 4, 3, 2, 1
9, 8, 6, 5, 4, 3, 2, 1
9, 8, 7, 5, 4, 3, 2, 1
9, 8, 7, 6, 4, 3, 2, 1
9, 8, 7, 6, 5, 3, 2, 1
9, 8, 7, 6, 5, 4, 2, 1
9, 8, 7, 6, 5, 4, 3, 1

8, 6, 5, 4, 3, 2, 1, 0
8, 7, 5, 4, 3, 2, 1, 0
8, 7, 6, 4, 3, 2, 1, 0
8, 7, 6, 5, 3, 2, 1, 0
8, 7, 6, 5, 4, 2, 1, 0
8, 7, 6, 5, 4, 3, 1, 0
8, 7, 6, 5, 4, 3, 2, 0

9, 6, 5, 4, 3, 2, 1, 0
9, 8, 5, 4, 3, 2, 1, 0
9, 8, 7, 4, 3, 2, 1, 0
9, 8, 7, 6, 3, 2, 1, 0
9, 8, 7, 6, 5, 2, 1, 0
9, 8, 7, 6, 5, 4, 1, 0

Shift and wrap:
7, 6, 5, 4, 3, 2, 1, 8
6, 5, 4, 3, 2, 1, 8, 7
5, 4, 3, 2, 1, 8, 7, 6
4, 3, 2, 1, 8, 7, 6, 5
3, 2, 1, 8, 7, 6, 5, 4
2, 1, 8, 7, 6, 5, 4, 3
1, 8, 7, 6, 5, 4, 3, 2

And if you're still striking out, there are a whole bunch of shift-wrap-split patterns I can generate.
 
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I don't understand the 9. The old chip only has 8 outs. Do you meant the bank select jumper? That's an input and shouldn't matter.

The design takes 9 inputs--I0-I6 for the truth table itself, 1 for table select and 1(I8) for tristate control. 8 outputs is correct however.

If I understand what you're saying, you'd like the outputs and inputs to be consecutive, with perhaps a split/wraparound, or at least mirror the original 82S123 layout as closely as possible.

I'll see what I can do.

P.S. It was a bafflement why Signetics started numbering their address lines with 0, but did their data lines with 1. Had me scratching my head wondering if my eyes were fooling me.
 
You got it. Try to keep them ordered (splits are fine), or one wraparound. Reversing the order works OK too - I can 69 the chips. The random shuffle was just going to be a mess of vias and spirals.

Numbering addresses from 0 makes some nerdy sense: you get the memory address by summing 2^n for each pin number n. Outputs are just a collection of bits so you can count from 1. Still, I'd have numbered both from 0 if I was doing it.
 
How's this--picture the 22V10 upside-down:

Code:
                            Chip diagram (DIP)

                             ._____    _____.
                             |     \__/     |
                         CLK |  1        24 | Vcc
                             |  2        23 |
                          a0 |  3        22 |
                          a1 |  4        21 | o8
                          a2 |  5        20 | o6
                          a3 |  6        19 | o7
                          a4 |  7        18 | o5
                          a5 |  8        17 | o4
                          a6 |  9        16 | o3
                          a7 | 10        15 | o2
                         /ce | 11        14 | o1
                         gnd | 12        13 |
                             |______________|
 
Much better! I was able to put it all on a single layer (excluding the ground plane). That should make it easy if anyone wants to etch one at home.

Note that I reassigned all the address pins. You'll need to recompile for the new arrangement.

Give it a look over. If it's good I'll upload it to the fab.
 

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Is this it?

Code:
      ._____    _____.
      |     \__/     |
  CLK |  1        24 | Vcc
   a6 |  2        23 |
      |  3        22 |
   a5 |  4        21 | o7
   a0 |  5        20 | o5
   a1 |  6        19 | o6
   a2 |  7        18 | o4
   a3 |  8        17 | o3
   a4 |  9        16 | o2
   ce | 10        15 | o1
      | 11        14 | o0
  gnd | 12        13 | a7
      |______________|

If so, I'll run a simulation to make sure everything comes out right.
 
Well, you got it right, but when I went to double check everything I realized I mirrored the bus connector! There's always another bug.

One more time, v0.5.
 

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I'm using CadSoft EAGLE Light. http://www.cadsoftusa.com/

It's popular for hobby use. It's a good EDA at this price (free for nonprofit use, $50 for commercial), although the Light version limits you to small 2 layer boards. There are much more powerful ones for much more money (thousands to tens of thousands), and there are also some pretty good open source ones (KiCAD, gEDA, others) that don't have any limitations and are completely free.
 
A lot of CAD software does. Linux/unix is pretty popular in the engineering world, and especially in the hobby engineering world. I think CadSoft knows that they're growing their next crop of customers by giving away free Light versions to hobbyists on all platforms. Hey, it worked for me. :)
 
Okay then, is this it?

Code:
      ._____    _____.
      |     \__/     |
  CLK |  1        24 | Vcc
      |  2        23 |
      |  3        22 |
   a0 |  4        21 | o7
   a1 |  5        20 | o5
   a2 |  6        19 | o6
   a3 |  7        18 | o4
   a4 |  8        17 | o3
   a5 |  9        16 | o2
   ce | 10        15 | o1
   a6 | 11        14 | o0
  gnd | 12        13 | a7
      |______________|

If so, I'll burn a GAL and verify that the result matches the PROM.
 
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