@Chuck(G): How hard is it to assign the pins manually? The random order is going to make the board look like a plate of spaghetti.
@digger: Chuck did the hard bits, dumping the ROM and probing the board, and coming up with a PAL program. It's pretty easy for me to design a new board when I know exactly what to make.
Pulling the copyright notice is just a practical matter. Including it in the PAL would be difficult. I do plan to give a shout out to him on the silkscreen on the boards. I'd love to get his blessing beforehand if we can track him down. I spent a while digging, but I can't find him.
The wizardry isn't so arcane once you know what's going on. Here, have some free knowledge:
The original 82S123 and the replacement 82S147 are parallel PROMs. The 82S123 is a 32x8: 32 memory locations, 8 bits each, AKA "256 bit". The address lines are A0 through A4 - 5 lines, thus giving us 2^5 = 32 addresses. You set each of those pins high or low, the chip looks up that memory location, and outputs the 8 bits on O1 through O8.
The 82S147 is a 512x8 (4kbit). The bus correction kit connects A0 through A4 into the same locations as the original chip. If we hardwired A5-A9 to ground and burned the original 32 bytes to the first 32 cells in the new chip it would work exactly the same. Instead it connects A5 and A6 to something on the 16-bit AT&T bus. I don't have a pinout so I have no idea what it is. But we now have 7 bits (128 memory locations) that are looked up to generate the 8 outputs. Since A7 is hardwired to ground, we have [128 bytes data] [128 bytes inaccessible] [128 bytes data] [128 bytes inaccessible] - the inaccessible parts are the text sections. A8 is connected to the jumper so you can manually choose the first or second 128 bytes of data.
Chuck thinks the purpose is to emulate some simple logic gates, and I think he's right. Basically if you have a small number of inputs into your logic network (Like 5-7, as we have here), and a small number of outputs (8 or fewer), you can just precompute all the outputs and burn them to a ROM. It's a neat hack.
The 82S147 is a "Bipolar" chip. that means "Bipolar junction transistors", used in Transistor-Transistor Logic == TTL. It's not very efficient with power, but it's quite fast for its era. In this case it's 45ns - set your inputs and in 45ns or less the outputs will be ready. That's about 22MHz, but there's a little more lag while it charges up the bus lines and the gates on any other chips, and we MUST be ready before the next clock. Still, it's plenty fast for an 8MHz bus.
Our replacement needs to be equally fast. EEPROM is based on CMOS, which came along later and is tremendously more efficient, but quite a bit slower. Of course, everything gets faster with time, so EEPROMs were getting faster... But lately parallel ROMs are considered obsolete and everything is going serial. Parallel EEPROM was just starting to get into the speed range that we need, but now it's being discontinued. Unfortunately the really fast stuff is already gone, probably because it was never in widespread use.
The other requirement is signal levels. CMOS == "Complimentary Metal Oxide Semiconductors". Complimentary means they use high-low pairs of transistors which greatly reduces leakage. The Metal Oxide Semiconductor part means field-effect transistors - MOSFETs, notice the MOS. The Field Effect part means the Metal Oxide insulates the transistor gates from the Semiconductor junction. Instead of constantly flowing current through the gate, it just charges up and the presence of the electrical field switches the transistor. That's great for power consumption, but it also means the gates require relatively high voltages to generate the field.
For a High level, TTL outputs guarantee 2.6V output, and require 2.0V (and high current compared to MOS) input; the difference gives you some noise margin. Early CMOS is about 3.8V in and out. While the open-circuit voltage is high enough, early CMOS didn't guarantee enough current to reliably drive TTL inputs (in practice it usually works). The hard part is the TTL outputs were hopelessly undervolting the CMOS inputs. In the 90s CMOS improved a lot, and practically all new chips are now specified to be compatible with TTL levels. Thus far all the replacement chips I've looked at are TTL compatible, but we still have to check.
So! What do we use to replace the chip?
EEPROM (easily reprogrammable) was my first thought, but Chuck's right: all the parallel EEPROMs 45ns or faster are gone.
PROM (cheap, but you only get to program them once) is still available. Atmel makes a 45ns chip that will work.
Flash (huge sizes for cheap!) is also available. Atmel has a 1Mbit 45ns chip that will work.
Chuck suggests the PAL / GAL. A PAL is a programmable logic array on a chip, which is exactly what the 82S123 was emulating! So we've come full circle. We just program the gates in the PAL to give the same combination of outputs given a set of inputs. It gives the same result as the ROMs, but it's really fast, around 3-5ns. I don't know how it works internally, but I'd guess it loads the flash into configuration registers on powerup.
Which is best? To me the flash looks easiest, but that's just because I'm familiar with them and I've never used a PAL. I think Chuk has done a lot more of this than I have so I'm deferring to his opinion, and since he's able to compile the program for the PAL it's no imposition on me either way.
So now you know, and knowing is dangerous.