Update - I've been chipping away at this, and so has Ian and his team on Dangerous Prototypes (DP). The DP XT/IDEv2 board, which is a 100% CPLD implementation, has gone to the board house. It's main advantage is cost - the board is only a couple of dollars, and the BoM is probably only another $10-15. It is mostly SMD based but this isn't as much of a problem as it sounds, with zero experience I soldered only up no problem.
Anyway, for compact-flash, as mentioned previously it is difficult to produce this in a board small enough to be cost effective. However I've got a first-cut of a board with both CF socket and 40-pin IDE header(see attachments). This is a direct decendent of the DP board, itself depending on the amazing work of the original of course. Changes:
- added the CF socket
- removed IRQ header
- replaced through-hole 28C64 with SMD part
- extended DIP switch to 12-way and integrated the remaining jumper header functions on to it
- changed DMARQ PD to 5.6k
- changed IORDY to 1k PU
However in order to route this board the 3.3V lines are 6 mils only, ground VCC + GND are 12 mils. I'm not sure that's really enough.
The idea is that the CPLD code will be compatible with the DP versions (standard or 'Chuck-mod'), and BIOS wise it will be compatible with either the XT/IDE Universal BIOS or Alan's future memory-mapped IO version for enhanced read & write performance.
Cost wise it should be similar to the DP version. CF header isn't cheap but SMD 28C64 offsets some of that.
Any comments very gratefully received... this is my first attempt at anything in Eagle so it's very probably littered with issues!
Eagle files are here.
Anyway, for compact-flash, as mentioned previously it is difficult to produce this in a board small enough to be cost effective. However I've got a first-cut of a board with both CF socket and 40-pin IDE header(see attachments). This is a direct decendent of the DP board, itself depending on the amazing work of the original of course. Changes:
- added the CF socket
- removed IRQ header
- replaced through-hole 28C64 with SMD part
- extended DIP switch to 12-way and integrated the remaining jumper header functions on to it
- changed DMARQ PD to 5.6k
- changed IORDY to 1k PU
However in order to route this board the 3.3V lines are 6 mils only, ground VCC + GND are 12 mils. I'm not sure that's really enough.
The idea is that the CPLD code will be compatible with the DP versions (standard or 'Chuck-mod'), and BIOS wise it will be compatible with either the XT/IDE Universal BIOS or Alan's future memory-mapped IO version for enhanced read & write performance.
Cost wise it should be similar to the DP version. CF header isn't cheap but SMD 28C64 offsets some of that.
Any comments very gratefully received... this is my first attempt at anything in Eagle so it's very probably littered with issues!
Eagle files are here.
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