Ibm 5161 & dma?

[IBM Portable PC]

Obviously it works with the IBM HDC, what about other cards requiring DMA like a Compaticard IV FDC etc?

Strangely, most of the 16 bit ISA (not 8 bit) ISA bus expansion options in later years could not be used with cards requiring DMA!?

 

[IBM Portable PC]

It looks like DMA may be fine, however bus mastering devices/controllers (do they exist in 8 bit ISA?) will be an issue?

 

[sergey]

It looks like DMA may be fine, however bus mastering devices/controllers (do they exist in 8 bit ISA?) will be an issue?

XT bus didn't support bus mastering. It was added with 16-bit ISA.

 

[Beerhunter]

XT bus didn't support bus mastering. It was added with 16-bit ISA.

Not until Micro Channel, and later still EISA, surely?

 

[Chuck(G)]

No, there are bus-mastering 16-bit ISA devices. The problem with 8-bit is that there's no real way to grab the bus. Pin D17 (MASTER) on the 16-bit bus allows this, but even so, the sequence of events is a little arcane (DRQ followed by DACK, followed by MASTER).

 

[cr1901]

No, there are bus-mastering 16-bit ISA devices. The problem with 8-bit is that there's no real way to grab the bus. Pin D17 (MASTER) on the 16-bit bus allows this, but even so, the sequence of events is a little arcane (DRQ followed by DACK, followed by MASTER).

Not that I know anything about ISA bus mastering (I only know enough to build a simple card lol), but what's 'arcane' about waiting for ACKnowledgement after sending a ReQuest?

 

[pearce_jj]

Basically ISA Bus Master is a bit of a bodge making use of the cascade channel on the DMA controllers as implemented in the PC/AT (since the DMA controllers could already be bus master) to allow an ISA card to then become master. The main problem is that there is no safety mechanism - once MASTER# is asserted, the CPU enters high-Z state until MASTER# is released. Which could be never.

 

[Beerhunter]

No, there are bus-mastering 16-bit ISA devices. The problem with 8-bit is that there's no real way to grab the bus. Pin D17 (MASTER) on the 16-bit bus allows this, but even so, the sequence of events is a little arcane (DRQ followed by DACK, followed by MASTER).

I just rad the tech. ref. and having done so, realised why one doesn't see AT Bus Masters. BTW, IIRC the AT DMA doesn't work very well anyway and so most transfers were done via the processor.