I decided I had let this thing sit around and collect dust long enough. I've been collecting ideas over the past several months, and now I have a somewhat-working Z8002 system. I have to finish up some odds-and-ends on the hardware, then begin writing an operating system.
So far, the system has the following configuration:
CPU board: Z8002 @4.0MHz, oscillator, buffers, diagnostic LED panel interface, CPLD and MMU SRAM.
SIO Board: Z80-SIO/2. Only has one serial port right now.
ROM Board: 2 sockets with 27c256 EPROMs
RAM Board: 4 128kx8 SRAMs
DISK Board: IDE interface, WD37c65 Floppy controller, Intel 82c54 timer
All the boards are made from Radio Shack 2200-hole pad-per-hole boards, and plug into a recycled VME backplane. It is not VMEbus, I developed my own bus and adapted it to the VME connector pinout.
Perhaps the most interesting part of the system is the MMU on the CPU board. I got this idea after reading about the SWTPC 6809 system. The MMU on my Z8002 card allows memory to be mapped in 4K pages. It supports a total of 1MB of memory. Upon reset, it is disabled, and the upper 4K of EPROM appears at address 0x0000. The EPROM code then sets up the MMU and enables it. The only problem with the current MMU design is when it is 'disabled' to write page information to it, address lines A19:A12 go high, causing the upper 4K of EPROM to appear at 0x0000 again. This is not a problem right now because I have the code that writes to the MMU at a fixed location in the EPROM, and I always keep the upper 4K mapped to address 0x0000. This makes the usable memory 60K (0x1000 - 0xffff), but I will just design my OS around the limitation. I am out of board space to make any design changes to the MMU.
There is still a lot of work to do, but right now I am happy I can write my test programs on my Linux PC, dd them to the floppy disk, and run them on the Z8002 from the ROM monitor.