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zilog z8002 cpu

pine-koan

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Oct 26, 2009
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Hello everyone, I am building a small board with a Zilog z8002, some memory, etc. I found two Z8002 data books in .pdf on bitsavers, but each describes the z8002's reset behavior differently: one says that it fetches the FCW, then the program counter, beginning at address 0004, the other says it only fetches the program counter value from location 0004.

Anyone know what the correct behavior is?

Thanks!
 
Anyone know what the correct behavior is?

I see the discrepancies also. I looked up some old code and it looks like for the Z8002, the Flag and Control Word (FCW) is fetched from location 0002 and the PC is fetched from location 0004.

The only correct description I found was on p. 7-3 of the Z8000 CPU Technical Manual dated January 1983. But even in that book fig. 7-2 showing the Program Status Area on p. 7-5 seems incorrect for the Z8002 as far as the Instruction Traps. The interrupt address info appears to be correct in that table.

I really liked that old chip and am glad you are playing with one. Let me know if I can be of help. There were four of them in a loosely coupled architecture in a re-design of a RADAR used in the F-111.
-Dave
 
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Hi
I interpret it to indicate that it loads the FCW from location
2 and then loads the PC with the vector at location 4.
It says:
"After reset* is negated, the CPU reads the FCW from memory address 2
and the PC from address 4 using status 1101."

I see that as being clear.
Do know that you need to drive the HICR bits while reset is low unless
you use the default with RSP0.
Dwight
 
Thanks to both of you for clearing that up. The manual(s) I have here only say the z8001 loads the FCW from location 2. They go on to explain the z8002 loads the PC from memory address 4, but say nothing about it loading the FCW.

I'm just getting started with this. I have the CPU, latches and buffers, SRAM, EPROM, and clock generator all wired up on a proto board, and I put all the 'glue' logic in a Xilinx CPLD. Tonight I'm going to try and write some code to get it to write to an I/O port. My earlier attempts failed, and I noticed the N/*S pin was always high, this would be the correct behavior since my EPROMs were programmed with '0000' at location 2 (and N/*S is the complement of the bit in the FCW).
 
You are correct. Typically a FCW of 4000H is used at initialization.

There were some really neat I/O chips that went with the family such as the 8030 Serial Comm Controller, a dual UART with a built-in baud rate generator. And the 8036 Counter/Timer and I/O chip. These I/O chips interfaced with the Z8002 without need for any latches or glue parts. I would guess they are hard to find today.
-Dave
 
Hi
I found another document that seemed to indicate that
the Z8002 didn't read anything but the vector at 4.
I do have two olivetti M20 machines with Z8001s. There is a
CP/M-8000 that can run on these but it needs to run
in a 128K environment where the program and data
space are split into 64K each and it uses the status
word to determine which is being used at any time.
This is a little more difficult to do on a 8002 because
the only way to write with the processor is to the data
space.
You'd need a bank switching method of switching the
instruction 64K into data space and back. The M20 does
this with an address decoder based on the segment
being accessed. It had a lot of screwy mapping, partly
related to the way the video memory is mixed in
the physical space and partly to account for the need
to use the 128K for some applications.
For the 8002 you'd need to use a
bank switching method of some type.
As I recall, most of the code is written to run in the
same mode as the 8002. I'm sure that BASIC is like that
but not positive about the CP/M.
Anyway, get some code working first than you can play with
such stuff.
Dwight
 
This is a little more difficult to do on a 8002 because the only way to write with the processor is to the data space. You'd need a bank switching method of switching the instruction 64K into data space and back.
Dwight,
No, using the Z8002 version is very simple. It does have four status lines that can distingish between a 64K data space, a 64K program space, a 64K I/O space, and a 64K stack space which can be very handy, but for small applications, everything can share a single 64K space. Program space would need to be in the low address space to contain the Program Status Area vectors and program code usually in EPROM while the data space (RAM) could be in the upper part of the 64K space with some small space reserved for the stack at the very top of RAM.

Reading and writing is allowed for all spaces. No bank switching is necessary.
-Dave
 
Dwight,
No, using the Z8002 version is very simple. It does have four status lines that can distingish between a 64K data space, a 64K program space, a 64K I/O space, and a 64K stack space which can be very handy, but for small applications, everything can share a single 64K space. Program space would need to be in the low address space to contain the Program Status Area vectors and program code usually in EPROM while the data space (RAM) could be in the upper part of the 64K space with some small space reserved for the stack at the very top of RAM.

Reading and writing is allowed for all spaces. No bank switching is necessary.
-Dave

Hi Dave
I was talking about this particular CPM. It uses much of the 64K program space.
The data space is more sparcely used though. To implement something else,
one can do other things with the status bits as you have suggested. Still, if
one wants to have RAM in the program space, one has to find a way to map it.
Dwight
 
Dwight, there were some Z80/8080 to Z8000 translators. It might be fun to make a compact CP/M for a Z8002 based on the CP/M 2.2 source.

Just musing...I've got a couple of Z8002s here and was musing about fooling with one.
 
Hi
I've not made pictures of mine but there are a number of good shots
on the M20 web page:
http://www.z80ne.com/m20/
If you go to the pictures page and scroll to the bottom, they show
the Z8000 board that plugged into the M24 to make it run PCOS
applications. M24s were quite common here in the states ( I think
RS sold them ). The Z8000 board was not so common here.
They also made a 8086 card for the M20 but these are in the
same catagory as hens teeth.
Dwight
 
Dwight,
OK, now I see what you mean. I am very jealous that you have a working Z8000 computer. Do you have a photo of the M20?
-Dave

Hi Dave
I just had a fellow offer me a M20. Not price. I can forward it to you if you like.
email me at dkelvey at hot mail.
Dwight
 
Well, after some irritating hardware reconfiguration (who counts like 1,2,3,5,4.... why did they have to swap AD5 and AD4!!), it kind-of works. I have six Z8002s - one very old AMD one (ceramic/gold) and five PDIP Zilog ones. The AMD one works the best - when the board is powered up, the small monitor program I wrote comes up flawlessly. The Zilog ones are behave strange. When they are first powered up (cold), they execute several instructions, then go off into the weeds. If you wait a minute or so, then reset the board, they work. All five behave the same way. I really wish I had a way to test these chips, so I could verify whether my design is bad or not.
 
The Zilog ones are behave strange. When they are first powered up (cold), they execute several instructions, then go off into the weeds. If you wait a minute or so, then reset the board, they work.
This is a little strange. Do you have an adjustable power supply? Can you try it with 5.2 Volts applied? Are all CPUs rated for the same clock of 4 or 6 MHz?

In my application, I used the military grade Zilog ceramics and derated the clock and, at room temperature, I could run the Vcc down to about 4.2V on the CPU board. But your parts are 25 years old...
 
After several hours of hardware debugging, I figured out what was going on. In my CPLD, there is a one-bit latch on an I/O port that disables the EPROM so the SRAM occupies the whole 64k. Well, I was generating an IOREQ signal from the decoded ST0-ST3 lines, but forgot to qualify the IO select signal with R/*W and DS. So, whenever the latched address matched the I/O port address, as soon as ST0-ST3 had the I/O request on them, the latch would set, and only disable the EPROM if the low-order bit (D0) was zero.

With the AMD chip, or the 'warmed-up' Zilog chip, by the time ST0-ST3 were decoded the correct port address was present, and everything worked fine. When the Zilog chips were cold, the timing changed slightly, and the 'old' address would still be present when ST0-ST3 would decode to I/O, and this would cause the latch to be activated.

I changed the VHDL code, reprogrammed the CPLD, and now it's working fine, and all of my Z8002's are good.
 
I decided I had let this thing sit around and collect dust long enough. I've been collecting ideas over the past several months, and now I have a somewhat-working Z8002 system. I have to finish up some odds-and-ends on the hardware, then begin writing an operating system.
So far, the system has the following configuration:
CPU board: Z8002 @4.0MHz, oscillator, buffers, diagnostic LED panel interface, CPLD and MMU SRAM.
SIO Board: Z80-SIO/2. Only has one serial port right now.
ROM Board: 2 sockets with 27c256 EPROMs
RAM Board: 4 128kx8 SRAMs
DISK Board: IDE interface, WD37c65 Floppy controller, Intel 82c54 timer

All the boards are made from Radio Shack 2200-hole pad-per-hole boards, and plug into a recycled VME backplane. It is not VMEbus, I developed my own bus and adapted it to the VME connector pinout.

Perhaps the most interesting part of the system is the MMU on the CPU board. I got this idea after reading about the SWTPC 6809 system. The MMU on my Z8002 card allows memory to be mapped in 4K pages. It supports a total of 1MB of memory. Upon reset, it is disabled, and the upper 4K of EPROM appears at address 0x0000. The EPROM code then sets up the MMU and enables it. The only problem with the current MMU design is when it is 'disabled' to write page information to it, address lines A19:A12 go high, causing the upper 4K of EPROM to appear at 0x0000 again. This is not a problem right now because I have the code that writes to the MMU at a fixed location in the EPROM, and I always keep the upper 4K mapped to address 0x0000. This makes the usable memory 60K (0x1000 - 0xffff), but I will just design my OS around the limitation. I am out of board space to make any design changes to the MMU.

There is still a lot of work to do, but right now I am happy I can write my test programs on my Linux PC, dd them to the floppy disk, and run them on the Z8002 from the ROM monitor.
 
I dug this thing out the other day (can you tell I don't ever get rid of anything). When I last worked on it, the hardware had not changed since my last post about it. I had some Z8002s that could run at 6MHz, and the other day I found a 12MHz oscillator so I thought I'd try and run it at 6MHz. It works just fine at this speed, which makes it a little more useful. It still isn't a very fast machine. With the simple multitasking operating system I wrote for it, there is considerable slowdown when more than one task is running.
The 'operating system' has evolved from a simple diagnostic monitor program that would load from the floppy disk, to a multitasking operating system that supports up to 16 tasks and contains a simple unix-like file system. There are now two serial ports, so I can have two terminal sessions going at the same time.
The sad thing is in the time that has passed since I last worked on the hardware, Xilinx has discontinued the 5 volt XC9500 parts. Avnet only has 9572s left. The CPU board and the DISK board both use 95108s in PLCC84 package.
Does anyone know if there are other 5 volt CPLDs that are still being produced?
 
The sad thing is in the time that has passed since I last worked on the hardware, Xilinx has discontinued the 5 volt XC9500 parts. Avnet only has 9572s left. The CPU board and the DISK board both use 95108s in PLCC84 package.
Does anyone know if there are other 5 volt CPLDs that are still being produced?

Would an Altera MAX 7000 series work?
Digi-Key currently lists the EPM7128SLC84-15 in stock for $19
PLCC84, 2500 usable gates, 128 macrocells. That looks in the same ballpark as the XC95108 2400 usable gates, 108 macrocells.
 
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