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Is it possible to use only expansion RAM on IBM PC?

jwt27

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Quick question,

I have an IBM 5150 with the 256k board, all banks filled, and a 1MB card from Lo-Tech to max it out at 640k. This makes the memory on the mainboard essentially redundant, and I could use these chips in another computer too. Is it possible to run the 5150 with only the first 64k bank, plus the 1MB ISA card, and still have 640k total? From what I read, the BIOS requires all banks to be filled, but the Lo-Tech wiki claims that "the use of the boards does not depend on having a certain amount of memory installed."

Before I start pulling them all out, could anyone confirm if this is possible?
 
You don't have to pull any chips. Just turn off the 2nd, 3rd and 4th banks and go from there. :) If it works...

BTW, can you configure the 1MB card to start at 64K?
 
You mean disabling the on-board banks through SW1, but leaving SW2 set to 640k? Will give it a try...

And yes, you can enable each 64k segment separately on the 1MB card :)
 
From the APR84 edition of the IBM 5150 Technical Reference:

if75v3947rbc7489.png


That will be because, in the 5150, all four banks of motherboard RAM are permanently enabled.

In the move to the 5160, IBM changed that; the two RAM bank related switches in switch block SW1 are not only read by the POST, they also selectively enable/disable the second, third and fourth, banks of motherboard RAM.
 
That will be because, in the 5150, all four banks of motherboard RAM are permanently enabled.
So this is incorrect?

IBM PC

Switch block 1, near center of board:



  • Switch 3,4
  • ON,ON = One bank of memory
  • off,ON = Two banks
  • ON,off = Three banks
  • off,off = Four banks
 
The dip switches do appear to do something, but not as expected. I've set both 3&4 to on, SW2 for 640k, and enabled 64-640k on the RAM card, this results in a B098 201 error on boot....
 
Refer to the snippet of 5150 motherboard circuit diagram at [here]. The lines from switches 3 and 4 on switch block SW1 run to the 8255 chip. The 8255 is not involved in bank disable/enable. The lines run to the 8255 so that their state can be read by the POST.

BTW: The lines between 8255 port A and chip U24, the 74LS322, exist because, in the 5150, port A is also used to receive keyboard bytes from the 74LS322.

Contrast that to the snippet of 5160 motherboard circuit diagram at [here]. Not only do the lines from switches 3 and 4 on SW1 run to the 8255 chip, for reading by the POST, they also head off to sheet 3 where they are used to disable/enable RAM banks.
 
Quick question,

I have an IBM 5150 with the 256k board, all banks filled, and a 1MB card from Lo-Tech to max it out at 640k. This makes the memory on the mainboard essentially redundant, and I could use these chips in another computer too. Is it possible to run the 5150 with only the first 64k bank, plus the 1MB ISA card, and still have 640k total? From what I read, the BIOS requires all banks to be filled, but the Lo-Tech wiki claims that "the use of the boards does not depend on having a certain amount of memory installed."

Before I start pulling them all out, could anyone confirm if this is possible?

What the manufacturer may be claiming is that the *use* of the board is not dependent on a mobo that is maxed out in ram. This doesn't necessarily mean it can take the place of motherboard chips.

Some motherboards (non IBM) can only have their DOS ram maxed via an expansion card. IOW the system board is only built to take things up to say 256k ram, typically. Tandy 1000s are like that IIRC, a number of others.

How the bios can *demand* that chips hard wired on the mainboard be filled up isn't clear to me. The expansion bus has access to the same bus that the memory banks do. Many people will tell you that the memory map has to do with the way the bios sets things up, but it has more to do with the way things are wired together. It all starts at the uPs address pins.
 
How the bios can *demand* that chips hard wired on the mainboard be filled up isn't clear to me.
Where did you source the information that the 5150s 'populate motherboard RAM banks first' requirement is a requirement of the BIOS ?

... but it has more to do with the way things are wired together.
With the IBM 5150, that is the case.

Refer to the diagram at [here], which represents the 5150's data bus.

Because the four RAM banks on the 5150 motherboard are always enabled, the signals to chip U12 are such that U12 will always go into 'position 3' whenever the CPU reads an address within the address space of the four RAM banks.
If a RAM card is present that is also responding to addresses in that address space, then you end up with two things 'driving' the data bus simultaneously (i.e. bus contention), the RAM card and motherboard U12. Imagine the RAM card trying to drive data bus line D3 to a high state and simultaneously, U12 trying to drive the same line to a low state.
 
"Where did you source the information that the 5150s 'populate motherboard RAM banks first' requirement is a requirement of the BIOS ?"

I didn't. I was simply responding to a post. It seems to be a popular misconception though that the BIOS determines what goes where on the memory map. Rather routing traces on the mainboard from the cpu (or socket) to the ram banks is what assigns the memory addresses.

Those block diagrams don't tell me anything. The op wanted to know if the card would allow it's memory to substitute for chips installed in various banks (I hadn't read the wiki first, I should have). According to the manufacturer this seems to be what it's designed to do. I'm guessing that having chips installed on the mainboard and utilizing the card would create redundancy. Some computer do just that, intentionally, the one that comes to mind is the IBM Datamaster.
 
The op wanted to know if the card would allow it's memory to substitute for chips installed in various banks (I hadn't read the wiki first, I should have). According to the manufacturer this seems to be what it's designed to do.
Well, I would say, with the caveat that the banks have been disabled (which is not always the same as removing RAM chips).

It could be that Lo-tech tested the scenario in an IBM 5150 and found that it worked. If it did work, it is because the driver chips in Lo-tech' s 1MB RAM Board are winning the bus contention tug-of-war with motherboard chip U12. A TTL tug-of-war is not a game that people will see playing on my 5150. It could lead to premature chip failure.
 
The idea of the board was to expand whatever is fitted up to 640KB (and beyond, in some cases) bearing in mind there are 16-64 and 64-256 5150 variants. In the 5160 it seems the motherboard banks can be part populated, however evidentially in the 5150 all system board banks must be populated. BTW the card can only drive the data bus.
 
If I understand this correctly, the reason it doesn't work is because U12 is always enabled (hardwired?) for the first 256k. So if I were to remove U12, or drive pin 19 high to leave its outputs in hi-Z mode, this would disable the on-board memory altogether and would allow me to use the expansion card for the entire 640k, no?

BTW the card can only drive the data bus.
That's all a memory card needs to do, right? Does this have any other implications?
 
Pulling U12 will isolate the system board memory logic from everything else. I think it should work, as the CPU is interfaced directly to the ISA slot data bus via U8, which is then interfaced to the memory bus via U12. So pulling U12 should leave that part of the system disabled. But we need to look at the NMI circuit (memory parity errors).
 
BTW the card can only drive the data bus.

I don't understand what this could mean. The card will have to access the address bus before it can put anything on the data bus. This is the normal sequence of operation. My understanding of this stuff may be lacking, or just that I'm rusty, and I'll have to review the issue Modem7 brought up. But anything plugged into the expansion bus has access to both address and data buses, and it's for the manufacturer (and/or installer) to make sure there aren't conflicts.
 
I think what pearce_jj means to say is that the card is only 'passively' using the address bus: it never generates addresses itself, so it never puts anything on the address bus, so it never drives the address bus.
 
But we need to look at the NMI circuit (memory parity errors).

This would have to be disabled too, I guess? From what I can tell, parity checking is controlled by the 8255 (/ENB_RAM_PCK in the schematics), so this could be switched in software?
 
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