daver2
10k Member
Thanks guys...
6551 ACIA and MAX232 level converter schematic complete.
Dave
6551 ACIA and MAX232 level converter schematic complete.
Dave
There are some DRC errors on unused pins of the EEPLD (Atmel ATF1508AS for the glue logic).
The use of this device has made the 'glue logic' and the PCB much easier. I have kept all the flip-flops and latches external (so the BANK SELECT and SYSTEM latches are still 74LS273s for example). The EEPLD should just contain combinatorial logic. It also means I can make the odd error or two and maybe get away with it by reprogramming the EEPLD!
I think I will revert back to the idea of not bothering with the write protect feature and use the extra bit from the MMU register as an address line. PET memory will be accessed by setting the MMU register(s) up to $00 through to $0F.
Hope that answers your question?
Yep.
The SuperPET has two switches. One selects the processor and the other selects whether the SuperPET memory is write protected or not. Let's ignore the write protect switch for now and concentrate on the CPU switch.
This switch has three positions - 6502, 6809 and software programmable. The first two switch settings (6502 and 6809) should be obvious. The 'software programmable' setting does what it says on the tin and you can POKE to the SYSTEM LATCH ($EFF8) to select which processor you require (bit 0). If you leave the switch in 'software programmable' mode - power-up will select the 6809. You could then run a small noddy program to 'flip' back into the 6502 PET mode. Flipping the physical switch from 6502 to 6809 (or vice-versa) will cause the processor to change and a RESET to be invoked. As simple as that...
The MMU will not affect the operation at all until you activate it by writing a '1' to bit 4 of the BANK SELECT LATCH ($EFFC). This is similar to how the TPUG MMU works for OS-9 (see http://mikenaberezny.com/hardware/superpet/super-os9-mmu/ for more details).
I agree - MMU operation can freak you out... Imagine how my poor brain feels trying to design it (and I am still not 100% confident that it will work yet)! QDOS to the guys at TPUG though with coming up with their clever design. Their design kickstarted me into thinking that a more comprehensive scheme was possible.
Hope that answers your question?
Dave
(2) Outstanding issues:
2a) Clock circuit. Should I use the original 6502 CPU Phi0 clock - and generate the 6809 'Q' phase via 74LS123's? This should make the SuperPET2 add-on board fully compatible with every 8032 without any modifications.
2b) With the simplification of the project (!) this should permit most (if not all) of the 'glue' logic (e.g. address decoding etc.) to be incorporated into one or two PAL/GAL devices instead of a CPLD. Would this be considered sensible?
2c) With a reduction in the logic (and the move to CMOS memory and 6502 CPU devices) this should permit the 5V power rail to be obtained via the 6502 CPU socket instead of a flying lead. Comments?