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Well done demo.(y)

ROMulan 4.1 (revised) ROM Bank 8 through 15 are all versions of Basic 4.

Yes, I can feel the suction on you even from California! Hopefully, isolating the ROM and BASIC RAM with your gadget will help separate the issues and indicate some direction to proceed. Daver2 has been heroic so far.

Hi Desperado, Yes on the character ROM itself, and on the schematic wires they are named RA7,8 and 9 and then LSD0 through LSD6. ROM address A10 is connected to 'Graphic' which I think should be always HIGH after power up on the 3032. -dave_m

For graphics character set: poke 59468, 12 For text character set: poke 59468, 14 This will reset/set the 'Graphic' output signal from the VIA (UB15) to the upper address line (A10) on the character generator (UA3) to select the the desired character set.

There are a lot of tiny screws that hold the PCB to the rest of the keyboard. Check to make sure you are not missing some of them. Does anyone have a photo that shows the location of the screws? As I recall they are scattered all over the board.

Ask Steve Gray how to download his Edit ROM binary that supports an external NTSC monitor for a CRTC PET or search Steve Gray CBM Edit ROM and assemble your own binary.

Great work!

Daver2, The Addressing circuitry comprises the largest part of the PET system. I hope our man has a new appreciation of the power of the NOP Generator if used properly and throughly. His first usage of the NOP gadget on this PET missed the problem due to not checking all the address line...

Before you run a 40 column game on a 8032, you might want to run the program called CBM4032. It will use the middle 40 columns thereafter until the pet is reset.

Right, this will be a good test of bus integrity. If we later try a $55 OP Code pattern, we perform a harmless 'EOR Operand, X' operation and if we get 2.5 V on a data line, we know two adjacent lines are tied together.

Or Can we temporarily deselect the RAM with a jumper?

Is the RAM also removable in this PET?

Daver2, Now I’m thinking, the problem may be when Reading the bus. Do you think I should write then read to a RAM location, or reading from a Pettest ROM location with known data pattern like $55? -dave_m

I suspect the data bus lines. When running the NOP and ignoring the data bus, the CPU runs OK. I will create a simple binary that runs in the kernel socket. It will perform a ‘walking ones’ test. It will use SEL 9 as a scope trigger. It will do a series of Writes to memory at another empty...

Desperado, If you want, you can tack solder a short wire to the signal you want to sync the scope, and clip the probe to the wire for a hands free connection.

A sensible statement. Too early to change that chip. More testing needed.

Good troubleshooting. I’m sure you Changed the cap. Sometimes a bad socket will trick your continuity test. With sockets only use a light pressure with the test lead. Daver2 will know how to interpret that test result.

Desperado, Are both D8 and D9 on sockets? Sometimes when measuring continuity, pressing hard with probe will give positive result, but there is still intermittent when pressure removed. At least spray some contact cleaner into the sockets. We are running out of options.

That may be the period between E800-EFFF where only a few I/O addresses will respond. A11 turns off the 2716 pettiest chip. Can Desperado check to see if that time decay and 1.5V time is around 4 mS?