8800B front panel/CPU/IF mod

[Ragnarock]

Does anyone have an 8800B panel interface board that has a jumper between chip V pin 10 and chip A pin 4?

This wire and cut adds SMEMR to the gating of DEPOSIT, SOUT and PWR to produce MWRITE on the bus. I'm trying to figure out if this was a factory mod listed in some documentation I haven't seen or something the previous user did to get the CPU/Panel/IF to accommodate something special on the bus such as another master.

 

[snuci]

I don't see any modifications on mine. Hope this helps.

 

[Ragnarock]

That's a good looking front panel with a solder mask! Mine doesn't have one.
My question about the mod is in regard to the interface board that this front panel plugs into that sits on the S100 bus.

 

[snuci]

No jumpers/mods on that board either. I might say perhaps I have a later rev but they are both Rev 0s. Hope this helps.

 

[Ragnarock]

Very helpful, yours does not have the mod that mine has. Thanks

 

[hmb]

Very helpful, yours does not have the mod that mine has. Thanks

The logic generating the MWRITE signal shown on the 8800B schematic (pWR AND /sOUT) is identical to that used on most other S100 CPU boards, and qualifying it with /sMEMR should not be necessary in any properly working S100 system. My guess is that the previous owner may have noticed spurious signals on the MWRITE signal line during memory read cycles perhaps caused by noise on the S100 /pWR and sOUT signal lines, and added qualification with /sMEMR to chip A input 4 to minimize the effect of this problem. There is no problem leaving the mod in place... but it should not be necessary.

 

[Ragnarock]

The logic generating the MWRITE signal shown on the 8800B schematic (pWR AND /sOUT) is identical to that used on most other S100 CPU boards, and qualifying it with /sMEMR should not be necessary in any properly working S100 system. My guess is that the previous owner may have noticed spurious signals on the MWRITE signal line during memory read cycles perhaps caused by noise on the S100 /pWR and sOUT signal lines, and added qualification with /sMEMR to chip A input 4 to minimize the effect of this problem. There is no problem leaving the mod in place... but it should not be necessary.

That's what I was thinking because this system also has a terminator board like it was trying to solve some strange problem. I suspect the previous owner had this intermittent RAM issue and bailed out. It's so good that it will sometimes boot CPM. I've been excluding things one at a time and am down to these 4 boards - SIO, Front Panel, Panel I/F, CPU, Tarbell 2022.

Yesterday I spent configuring a Northstar Z80 board to power-on JMP to F800 where I've put ALTMON from the FDC+ EPROM onto a Tanner 64K board and it passed memory test for the first time so that definitely narrows it down to Front panel, IF, CPU.

It even booted CPM and after running SURVEY.COM the whole thing stopped and now nothing will run. I'm back to square zero and have already spent more weeks on this than I ever intended. I'm done with this battle, just too many unknowns and I could easily spend the rest of the year on it which I'm not inclined to do. After 8 years of restoring multibus, SS50, QBus systems, I have yet to get an S100 bus system running solidly. I need to start with better stuff.

 

[Istarian]

Given that S100/S-100 bus was apparently something of a pseudo standard prior to the publication of IEEE 686...

I'd say any system that wasn't working perfectly when it was built and used or which has been modified since might not behave well.

Any sensible person would probably want to take it apart and focus on getting the most minimal setup possible before getting too deep into troubleshooting.

You could look into getting a reproduction front panel and/or interface board? Then you could build it yourself and be fairly certain it wasn't the problem.