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A Homebrew Z8002

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Plasmo

Experienced Member
Joined
Aug 29, 2017
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Location
New Mexico, USA
I have four Z8002 dated 1979 for a number of years. I have forgotten where they came from and no idea whether they work or not. Recently I have built up a prototype board hacked from a Z280 pc board and managed to powered up a Z8002 and it seems to execute NOP test OK and can put data out over a serial transmitter, but when I tried a slightly more complex program to receive serial input and echo it back, it does not work consistently, the serial receiver seems problematic. After quite a bit of troubleshooting, I’ve decided my prototype setup is overly complicated that I need to start out with a simpler prototype then build it up gradually with more components.

I’m starting a new topic here to document my journey with a homebrew Z8002.
Bill
 
Do you want to PDF your current schematic and code and I will take a look - or are you just going to start again?

Or is the code still as per previous thread post #51?

Dave
 
The problem with first prototype was lack of documentation and shifting goalpost. It was something I put together from whatever convenient to prove Z8002 is working but then I changed my mind wanting to write a Z8002 monitor and work toward CP/M. The board schematic, CPLD schematic, and test code were barely holding together and not documented. It did prove my Z8002 are likely functional up to 3.68Mhz and the CPLD has capacity to accommodate bootstrap code and serial port.

For this second iteration I will document the design more carefully and start with just Z8002 and CPLD. I’ll add RAM and CF interface when the simple Z8002+CPLD is working.
Bill
 
Thank you for taking an interest in my homebrew project. This is what I have right now. It is just Z8002 and EPM7128S CPLD. The CPLD will provide 64, maybe 128 bytes of bootstrap code and serial transmitter and receiver. I’ll add RAM and CF later. I will provide the schematic of the prototype before power it on. The first test will just be Z8002 executing NOP instruction.
Bill
 

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This is schematic of the Z8002 prototype board. Mostly it is Z8002 signals connected to CPLD test points except RESET, CLOCK, and nMREQ. The test point signals are assigned in CPLD. The first CPLD design just provides NOP instruction (0x8d07) to AD(15..0) whenever nDS is asserted. It checks whether the CPLD signals are properly assigned and whether Z8002 is functioning.
Bill
PS, try to work up enough nerves to turn on the power! Probably will wait until tomorrow, although I’ve known to wake up 2am, went to work to turn on a prototype board. That was when I was young and foolish, now I’m just foolish!
 

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I assume you have run out of CPLD pins to wire up the N / notS signal from the Z8002?

I can't see anything that would make me concerned. As you say, it is pretty much pin-for-pin wiring between the Z8002 CPU and CPLD.

I developed a VME I/O interface card using wire wrap - and tested things as much as possible with a multimeter before taking the inevitable step of plugging it into a VME system to test (aka tune for minimum smoke). It worked first time!

I did find a fault with the original MULTIBUS 1 system that I was replacing whilst developing the CPLD - so fixed that at the same time...

I have a colleague who worked for a defence supplier. One of his colleagues developed a wire-wrapped VME card and did the same thing. Apparently the wire wrapping lit up like the New Your City skyline - until they all burnt out... Clearly, he didn't do his tests with a multimeter too well!

Dave
 
Thanks for checking the schematic. CPLD has plenty spare pins, so I’ll connect System/Normal signal to one of the spare pins.

Finally turned the power on after programming the CPLD with NOP instruction. Power consumption is 288mA at 5V. AD[15…0] is driven with 0x8d07 when nDS is low and RnW high. Each instruction is executed in 7 clocks; the 64k addresses are incremented by 2 every 7 clocks so A(15) toggled at 16 Hz with 3.68mhz system clock. A(15) is connected to a LED so it is flickering rapidly. It all seems to work.

I’ll reprogram the CPLD with serial transmit test next.
Bill
 

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I repeated the serial transmit test that writes a value to serial transmitter, increment the value, wait a while, and write new value to the transmitter and repeat. That worked well, but a similar test that read serial receiver and wrote back to transmitter won’t work at all. Like the previous prototype board, the program behaved erratically and power consumption changed depending on the serial value entered. Before I get too wrapped up chasing this problem, I thought I’ll post the successful serial transmit test. Attached are schematic of CPLD, the program that is in “ROMblab3”, and the screen captured Teraterm output.

Edit, “Txr” inside the CPLD is a library component I have used successfully for several year. It is basically a loadable shift register and associated state machine to transmit 8 bit, no parity, 1 stop bit.
 

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I see nothing wrong with what you have done so far, with the following observations:

If you are trying to read from the serial device, what is your logic like for interlocking the serial read and the ROM read?

You are currently not using nMREQ in the ROM access. This status signal should be LOW when accessing memory (ROM or RAM).

I would suggest adding nMREQ=active into the ROM buffer enable and nMREQ=inactive into the status decode for the I/O cycle for enabling the serial port read or write (although this latter suggestion should be 'belt and braces'.

With the current configuration (although you have not shown the receiver) you will get a data clash between the receiver and the ROM.

I may be jumping the gun here though...

Just reading up on the Z8k memory and I/O access cycles in: https://bitsavers.org/components/zilog/z8000/Fawcett_Z8000_Design_Handbook_1982.pdf to refresh my memory (no pun intended).

Dave
 
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Just done a bit more reading between meetings.

Technically, the Z8002 clock input pin is not TTL compatible. It is a MOS signal - so requires a much higher and lower drive voltage than a TTL output provides and the datasheets identify a maximum transition time of 20 ns.

I have generally ignored this myself, but...

Dave
 
If ST0-ST3 decoding is used for I/O operations, there is no need to check the status of the MREQ signal.

PS. The third line of the program should be 0x4000 instead of 0x0400.
 
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Believe it or not, I’m still diligently working on my Z8002 prototypes. I have bounced between two different prototypes and tried 2 different Z8002, yet still gotten the same perplexing results. The breakthrough came tonight that

INB RL1,81h

where 0x81 is address of serial port
Does not work on my Z8002, however

INB RL1,@R5

Where R5 contains the address of the serial port (0x81)
Works as expected

Very strange, possibly my early date Z8002 had errata about this bug? Anyway, now I understand this bug, I’ll plow ahead.
Bill
 
Interesting. I have checked my code for reading a character from the serial port and it refers directly to the address there. For my tests I am using an East German clone UB8002, which certainly does not have the best mask of this processor.

! getc
! input 1 byte from the PORT A
! return: rl0 --- read data
getc:
inb rh0, #WR0A
andb rh0, #0x01
jr z, getc
inb rl0, #WR8A ! RR8 Receive buffer
ret
 
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I’ve added a pair of RAM to my z8002 prototypes. The memory map is ROM from 0-$FF, RAM from $100-$FFFF. Serial port is in I/O space $81 data, $83 status. I set aside 256 bytes in CPLD for ROM space, but actual ROM size is limited to 128 bytes. Most test programs fit in 64 or 32 bytes. CPLD utilization is around 90%, depending on size of ROM. Schematic of CPLD is included.

The ‘echo’ program is a tiny program that delays few hundred milliseconds, reads the serial port, then echos back what it read, and repeat. The program works when serial input is INB RL5,@R6, but put out a constant character with INB RL5,81h. That constant character remains the same regardless of what I type.
Bill
 

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