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AIM 65/40 repair

No need to remove ROM, RAM or anything else. We have 'nobbled' the CPU data bus directly.

However, scoping the 'real' machines data bus will indicate if any bus contention is present.

Dave
 
If the CPU is executing NOP instructions, the SYNC pin (7) should be constantly pulsing once every two clock cycles.

You check the address lines. Look at A0 first and determine the frequency. This should be the CPU clock frequency/2.

Each higher address line should be half the frequency again.

Then check the address decoding/chip selection logic fir the ROM, RAM and I/O devices.

I am going on a business trip fir the remainder of the week, so message posting will be sporadic...

Dave
 
Thanks, it looks like it's broken

pin A0 (9) 20250414_233840.jpg pin SYNC (7)20250414_234609.jpg

Don't worry about it, this board was presumably dead so many decades - what's a few more weeks / months

Enjoy your business trip and easter weekend, and reply at your leisure and I will try to find out what's causing this chaos
 
daver2 said:
One is the single step logic (consisting of Z79 and one gate of Z30) and the other is the ATTN SWITCH from the keyboard.

Neither of these should be generating a /NMI after a power-up.

Check to see what is generating the /NMI (by checking Z74 pin 10 (should be LOW) and Z79 pin 9 (should be HIGH)).
Click to expand...
Z74 output is fine, Z90 pin 9 goes low. Some of the input signals of Z79 must be wrong

1744803582345.png

So then, /IOCS or RUN/STEP maybe

 
In fact, I was going to suggest checking the /NMI and /IRQ inputs to see if these are being activated (LOW). If so, they will affect the NOP generation waveforms obtained.

Dave
 
/IRQ appears to be ok, but /NMI is driven low and I don't see how or where. RUN/STEP seems to be software driven (by the system VIA?)

I wonder if there is some crosstalk between signals? If I trigger off the clock, the /NMI signal looks like this

20250417_001056.jpg
 
I am still on my business trip - so no access to anything...

Is it possible that the output from the VIA 'enables' the 'STEP' logic, and the default behaviour (with the VIA unprogrammed) is to enable the logic?

The clock (Phi 2) is certainly an input to Z29, meaning that all of the other inputs to Z29 are HIGH. Is this the case?

I will be back home tomorrow, so will have a look at what feeds the inputs to Z29.

Dave
 
daver2 said:
The clock (Phi 2) is certainly an input to Z29, meaning that all of the other inputs to Z29 are HIGH. Is this the case?
Click to expand...

Do you mean Z79? It appears that the VIA outputs are high by default. The SYNC and /IOCS are pulsing irregularly.

I looked at SYNC and the datalines directly and am not sure it's executing NOP instructions
SYNC
20250418_002225.jpg

Datalines tied to +5V
20250418_002313.jpg

All the datalines which are tied high are driven low every once in a while. Do you agree there should be nothing else driving the data bus?

I think I had wrong settings on the scope before, the /NMI goes low in about the same pattern as SYNC
 
Yes, Z79. Doo!

If an /NMI is occurring, this will cause the PC to be written onto the stack (i.e. a write on the CPU data bus will occur - and will drive all of the data lines). Any that are written LOW will pull down the voltage on the pull-up resistor (i.e. exactly why we put the resistor in there in the first place rather than a direct link to +5V).

I will look tomorrow to see if we can persuade this gate to not generate an /NMI.

Dave
 
Hi Dave
Thanks for the explanation, I was wondering how it would write data without being connected to the data bus.

Z79 is in a socket because it is one of the defective ICs I have found before opening this thread. Here is what was replaced:

I have replaced Z43, Z79 and Z83 and reconfigured the RAM to be only one bank. The replacements are all of SN74LS type.

The previous owner replaced/socketed Z16, Z29, Z48, Z82 (I don't know what was in there before)


20250418_093519.jpg

I have removed it and the CPU is now executing NOP instructions. What are the next steps? Try to get to the bottom of the wrongly generated NMIs?
 
Removing Z79 now means that the input to Z30 (on pin 3) is now floating.

The NMI logic may not be 'wrong' just triggering due to the presence of other fault(s)...

Now check the address lines again and make sure they are now correct. Follow the address lines through any address buffers (to make sure the buffers are working correctly).

Dave
 
After the address lines, look at the 16 decoded outputs from Z61.

The upper 4 address lines are decoded to form 16 outputs, with each output decoding for 4K of memory as it is 'scanned' by the NOP generator.

The outputs from Z61 should form the chip select lines for the ROM, RAM and the various I/O devices.

Dave
 
daver2 said:
Now check the address lines again and make sure they are now correct. Follow the address lines through any address buffers (to make sure the buffers are working correctly).
Click to expand...
The buffer for A12-A15 seems to be working, but the address lines...

daver2 said:
Look at A0 first and determine the frequency. This should be the CPU clock frequency/2.

Each higher address line should be half the frequency again.
Click to expand...
This is not the case, SYNC pulses high every two clock cycles, but the frequency of A0 is CPU clock/4
 
OK, I may have messed up my calculation! Assume A0 is correct at CPU clock/4.

I have had a good afternoon researching the AIM 65/40 schematic - so I have a lot of things for you to test now (when you have done the address lines that is).

Dave
 
Just checked on the PET - and A0 should be 250 kHz with a 1 MHz oscillator frequency for the 6502 and running NOP instructions.

Dave
 
Good news then, they look OK to me. They're at about 3V but that should be enough I believe.

What doesn't look ok are some of the Z61 outputs. In the present state there are a few that are high with low going pulses other others are low. But pins 2, 3 and 4 aren't high enough, they're only pulled up below 2V.

Don't know what I'm looking at in the schematic....?

1745086175587.png
 
So, just checking the schematic for the /NMI generation and bank switch.

There are tow (2) outputs from the SYSTEM VIA (Z5) that could seriously affect the operation of the AIM-65 if this VIA is not working correctly (or is not being programmed - or programmed correctly - by the firmware on the board).

The two (2) outputs are:

PB3 (Z5 pin 13) = /RUN / STEP and
PB2 (pin 12) = BSE.

PB3 controls the STEP and RUN logic. If this signal is HIGH, it means that a /NMI cycle is generated if the CPU is executing instructions in the address range $0000 to $8FFF (by default with wire link W11 removed). Accesses to memory above $8FFF will operate normally. When running a NOP generator, the SYSTEM VIA (Z5) will not be programmed. This means that PB2 and PB3 will be an input and hence the logic input to the subsequent TTL logic gates will be HIGH. This will cause permanent /NMI cycles to be generated to the CPU...

If you observed the same response when we were not running the NOP generator, it probably means that the ROMs are not correctly being executed, the SYSTE VIA is not being programmed, or the SYSTEM VIA is faulty.

Likewise - for PB2 - this signal selects which Bank Select mode is operational. Mode 0 is the AIM 65/40 mode and mode 1 is the RM65 mode. In mode 1 (PB2 = BSE = HIGH) the Debug Monitor ROMs ($Axxx and $Bxxx in locations Z65 and Z66) are disabled!

Dave
 
Post #57.

The outputs from a SN74159 (Z61) are open collector - so the outputs do not have a pull-up resistor.

The pull-up resistor is provided externally by the pull-up resistors on the pins of the Z60 gate.

My assumption is that switches 1, 2, 3 and 4 of S3A are closed. In which case Z61 pins 1, 2, 3 and 4 should have pull-up resistors (assuming the switches are really closed!).

The outputs from Z61 should be HIGH and pulse LOW when the inputs are in the correct address range. HOWEVER, only for Z61 outputs that have a valid pull-up resistor.

I have a small test clip that I use - which is an old plastic ball-point pen case with a probe tip and an internal 1k resistor with a flying lead that I can attach to the +5V rail. I can then use this probe (in conjunction with my oscilloscope) to see what is really going on (even if there is no pull-up resistor fitted). This situation sometimes happens on a keyboard matrix. An open collector IC is used to drive a key matrix - but the pull-up resistors are on the 'far side' of the keys - pulling the signals up to the input circuits of the logic. The open collector output driver then pulls the voltage LOW when a key is pressed and the output from the open collector TTL chip is driven. Just measuring the pin with an oscilloscope on its own is a futile operation and has caused needless open collector devices to be erroneously replaced...

Dave
 
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+3V is technically enough (TTL signal HIGH) - but I would expect the HIGH signal levels to be higher than that though...

Can you just measure the voltage at TB1 - making sure to get the connections correct - TB1/1 0V and TB1/2 +5V.

1745089893616.png

Dave
 
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