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Apple //GS: Is there a way to boot and run an Apple ][ 6502 OS in banks E0/E1 ?

george

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Apr 1, 2011
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Apple //GS: Is there a way to boot and run an (existing?) Apple ][ 6502 OS in banks E0/E1 in native CPU mode? No GS features are required. 1MHz clock like on previous Apple2s is perfect. The reason for needing this is because there are hardware features present in E0/E1 Mega II space which are unavailable to the emulation banks 0/1.
 
Studying further the docs I found out that 65C816 supports running emulation mode in banks E0/E1 (and in every bank) but the Apple 2GS ROM is unable to handle interrupts from banks other than 0/1. Is it realistic to hook the interrupts and make something like a small hypervisor residing out of E0/E1 and translating interrupt requests between 6502 software running in E0/E1 and the Apple 2GS ROM?
 
I am trying to achieve higher compatibility of the legacy Apple2 peripheral cards and 6502 software under Apple //GS. For example I discovered that peripheral cards that use *INH signal to map their own space appear in banks E0/E1 but not in banks 0/1 therefore remain undetected by the 6502 software.
 
What software in particular? Many of the incompatibilities can be resolved by setting the CPU speed to "Normal"/1Mhz. By default the Apple IIgs uses shadowing to make banks E0/E1 appear as banks 00/01 to 8-bit Apple II software. The Apple IIgs hardware reference and various open source IIgs emulators shows how the shadowing works.
 
What software in particular? Many of the incompatibilities can be resolved by setting the CPU speed to "Normal"/1Mhz. By default the Apple IIgs uses shadowing to make banks E0/E1 appear as banks 00/01 to 8-bit Apple II software. The Apple IIgs hardware reference and various open source IIgs emulators shows how the shadowing works.

Speed is irrelevant in this case. The shadowing works only in one direction from banks 0/1 to banks E0/E1 and not vice versa you can try it on a real //GS and on an emulator for example in a HGR page. But with the cards that map space via *INH signal no shadowing occurs at all even if CPU writes to this space though such shadowing would have been completely insufficient with a bank switched memory in the D000 region.
 
Further investigation lead to a conclusion that stack and direct page cannot be moved out of bank 0 due to CPU limitations. Therefore my answer to my question in the first message of this topic is unfortunately negative.
 
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