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CAD tool for DEC style mixed logic

It looks like something is wrong somewhere with either the accumulator or the ALU logic (at a guess).

Everything seems OK with d01 up to the CMA instruction. CMA doesn't seem to complement the accumulator for some reason...

I haven't got any time to look into it further now - but I will later in the week. I am not sure why anything has changed on my machine though...

EDIT: I did find an old post of the simulator source and a picture of it running CHEKMO over at #45

EDIT: V0.5 is here: #61

Dave
Thanks Dave.
The V0.5 simulation works well and CHEKMO II runs ... OK runs may give the wrong impression ... works is more appropriate. :)
Both Logisim and the LD12 simulation are very impressive and I now feel reassured that a PDP-8/s re-implementation and simulation is within reach.
I will continue reading the book "The Art of Digital Design" with the knowledge that I now have the tools and a template to attempt a PDP-8/s.
Thanks to all who responded.
 
For an 8/I emulator that's very slow (but highly accurate), here's my Verilog implementation which can be run using Verilator.


The model has been tested on real hardware as well, using a PYNQ board connected to a PiDP-8/I front panel. Of course, synthesizing for an FPGA means accurate timing; way faster than Verilator.

Still have a dream of emulating an Omnibus machine as well as the PDP-12. Maybe someday...
Thanks Kyle. I have looked at your Verilog implementation before. It is a nice approach similar to Paul Koning's CDC 6600 simulation done in VHDL. By implementing all the 8/I modules in Verilog you could simply instantiate the appropriate set of modules and wire them up like the real thing. It should provide a very accurate implementation of the 8/I. The difficult bits are where the design crosses into the analog domain - e.g. core memory. Synthesizing for an FPGA is an additional bonus. At the moment I am trying to get my head around traditional logic design using 74LS series logic even though a 8/s in VHDL would be much easier.
 
So I now have to find out why 0.5 runs and 0.6 doesn't...

You also need to be aware that you can do things with TTL logic that you can't do in VHDL. For example cross-coupled NOR gates to make an SR flip-flop.

I converted the Apollo Guidance Computer schematics to VHDL and found that out the hard way! I had to introduce clocked D type latches at appropriate points throughout the logic to turn the design from pure logic gates into a clocked design. That took me a while - but I did get it working...

Dave
 
So I now have to find out why 0.5 runs and 0.6 doesn't...
I was curious about that too and compared the two versions of PDP8-LD12.circ using BeyondCompare (a graphical diff tool). Unfortunately it appears that when Logisim saves a file after a small change it does not preserve the structure of the original file with just the differences due to the change. This means that side by side comparison or diff tools are useless to find out what has changed.
 
Not yet, but I have found a completely different folder on my development machine containing V 0.5 - and I am now convinced that is the correct version that I tested and posted.

I am just thinking that I was 'tinkering' with V 0.6...

I have an image of the V 0.5 logic, so I will compare that with V 0.6 tonight. I may even have found the paperwork with the 'tinkering' I was doing. I don't think I ever released this version, so it may be buggy...

Dave
 
I think the error has come from the computation of S2 and (possibly) CIN.

I appear to have missed a gate off the computation of S2 associated with the TTY modification (G17). I suspect the MAINDECs aren't testing this.

I must have reviewed the TTY schematics post V 0.5, identified a fault, fixed it in V 0.6 - but never actually got around to testing it fully!

I may now have some signals inverted?

I will have a look over Christmas - although I will go back to the 'original book' first...

EDIT: I think I have found it. I have just made a modification and MAINDEC d01 now seems to run OK. I will test all of the other MAINDECs tomorrow (and give CHEKMO a game)...

If this is OK, I will update the file on my Google Drive and let you know when it is available.

Dave
 
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Jack,

I could have sworn that I uploaded the PCB Gerbers...

Anyhow - the PCB has now been uploaded along with the current construction manual.

I have the interconnecting cables to make and then it is inserting devices and testing.


Dave
Thanks - I knew you had uploaded some files a while back but got the impression they weren't quite finalized regarding switch(?) placement. I'll take a look and see if I can order a set before Chinese New Year (I move slowly these days).

Jack
 
Jack,

I have a fully populated front panel at home. It just needs the cables making and testing. That will show up any PCB flaws, but I haven't found any during construction (so far)...

All of the placements worked out fine. It was a good job I got my son (a mechanical engineer) to check over my work before getting the PCB made though. He found a few errors...

Dave
 
I think the error has come from the computation of S2 and (possibly) CIN.

I appear to have missed a gate off the computation of S2 associated with the TTY modification (G17). I suspect the MAINDECs aren't testing this.

I must have reviewed the TTY schematics post V 0.5, identified a fault, fixed it in V 0.6 - but never actually got around to testing it fully!

I may now have some signals inverted?

I will have a look over Christmas - although I will go back to the 'original book' first...

EDIT: I think I have found it. I have just made a modification and MAINDEC d01 now seems to run OK. I will test all of the other MAINDECs tomorrow (and give CHEKMO a game)...

If this is OK, I will update the file on my Google Drive and let you know when it is available.

Dave
Thanks Dave for your help with this. The simulation is impressive.
 
I have the interconnecting cables made up now so I will update the construction manual on Saturday and post the update.

Inserting ICs and testing next...

Dave
 
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