Hugo Holden
Veteran Member
Exactly right and one other feature to keep in mind about TTL sevices, while their outputs are good at sinking current and pulling a solid low state (the lower output transistor in the output stage, when conducting acts as a low value resistance) their pull up is very very weak.
Much of the pull up current sourced from the 5V supply comes from the input currents from the input pins of other IC's connected to the output pin. This is why when the output pin is in the logic high state (in the typical 3 to 4V region) you will often see other small pulses superimposed on the signal in TTL circuits, because in that high logic state it represents a relatively high impedance and is more vulnerable to interference and variations in the input pin currents of other IC's conducting switching operations.
If the design requires the logic high voltage in TTL to get closer to +5V it requires a pullup resistor gets added to the output pin. For example it would be normal practice if you wanted to feed the output pin of a TTL into the input pin of a CMOS device, you would use a pullup resistor.
This is quite unlike CMOS, it has a symmetrical output stage and the pull up toward +5V is equally hard as the pull down toward zero volts, and because of that, its easy to see on a scope that when there is a logic high it is a clean relatively noise free signal, at least as good as the +5V supply and fairly close to 5v.
The reason for this in TTL, is because the chips were designed on the basis that decoded control signals were generally logic low and global device control signal inputs were logic low, so that the Fan out of the TTL output pin could drive as many TTL inputs as possible to a low logic state. It is a system of active low logic. This is also why many auxiliary TTL IC's have control signals configured for low active states. For example /E pins on ROM's, /CLR inputs on counters, or /CLR or /SET inputs on flip flops etc etc.
The TTL Circuit designer's Brains, all worked in active low, so for example when they reached for an AND gate they often didn't want the AND function for positive signals, they wanted an OR gate with negative active inputs and a negative active output, they had De Morgan's theorem imbedded in the brain to convert between various forms of gates.
You will see with a lot of TTL logic circuits, it only becomes possible to figure out how they work, in some cases to find out what the designer intended, if you convert gates such as NAND & NOR into their DeMorgan equivalents with negated inputs.
In many circuit positions though, the TTL designer would want a gate output to respond to combinations of high inputs, for example when gating signals from the output of counter arrays, to create a reset pulse etc. There are no hard and fast rules that say you cannot use TTL for positive input logic combinations to some gates or devices. It is more of a design theme, where some decoded output, from an output pin tended to be an active low. In TTL, many of the detected logic conditions may well be high state conditions on the input signals to gates or gate arrays, and the outputs from the gate arrays are active low, just like the 74154 being a fine example.
Then CMOS came along where the input pins sourced or sunk negligible input currents and people started designing with positive or negative active logic in mind because the effective fan out of the device worked equally well for both. And then control inputs on many devices like CMOS flip flops then became positive or high going, to be deemed active. For example a typical CMOS D flip flop such as a 4013 has high active set & clear inputs, but the TTL 7474 D flip flop has low active set and clear inputs.
