Ah, I think I have found it by looking at your photographs and tracing out the PCB tracking. This is what I think the circuit looks like:
40C is the 8 MHz clock and 80C is the 16 MHz clock.
The J1 link is installed (i.e. that machine is 40 columns) shown in red above.
The 'other' end of J1 and J2 is commoned by a PCB track (I have shown this in black).
The common part of the J1/J2 link (I am guessing here) is connected to UD2 pin 11. Don't forget that that the modification cut pins 10 and 11 of UD2 (thus isolating the gate from the circuit) and the 'solder blob' bridged the PCB tracks connected to UD2 pins 10 and 11 (as I have shown above in red).
The 'original' circuitry (with the UD2 gate in circuit) outputted /(CLK16/CLK8) (notice the subtle placing of the NOT '/' symbol and the parentheses).
The modified circuitry removed the UD2 gate and the circuit now outputs CLK16/CLK8 (a non-inverted clock signal from what it was previously).
The original schematic appears to have been incorrect anyhow - and, therefore, the factory modification and solder blob did not make sense. The above does, however, now make sense to me - and accounts for why the solder blob
IS important...
Issue closed (to me at least)
!
Just a little note on the way I work. I generally ask for signals on pins that provide confirmatory checks. For example, I will include +5V and GND pins in the list of IC pins to check - to make sure that logic HIGH and logic LOW are reported. Sometimes I ask for checks on signals at 'both ends' of the PCB tracks to see if the same signal is reported back to me. If not, this either indicates that I incorrectly asked for the measurement points, the wrong points were measured, the PCB tracking is not intact, we have the wrong schematic for the particular board or, as in your case, the schematic is incorrect. This is where I stop and we do a bit more investigation as to which of the above applies.
Dave
...
proof attached
if you watch severance
