GWiley, thanks for the comments.
The first comment on the 12 bit count, I just was not thinking. Just had to change the right counter D3 from zero to one.
The second comment, changed the count enable lines to just a pull up resistor.
The updates look good regarding both of these.
To make the following easier, let's say the '163 chips are numbered U1 on the left, U2 in the middle, U3 on the right.
The third comment I had to think about for a while. I may not have this correct. I used a NAND of the right carry out (TC) and the right Q0 to control the LOADs.
The J? Clock Output should come from U3 pin 14 (Q0) so it is glitch-free. That's the only necessary change.
The updated schematic with the NAND will count as you intend it to do. However, you really only need to invert the U3 TC (pin 15) and feed that back to the load inputs. This is because when U3 TC is one, U3 Q0 will also already be one. U3 pin 14 (Q0) will actually go to one at count 0xf00, decimal 3840. So, the schematic as it is will count in the sequence you want, but only need U3 pin 15 inverted going to pin 9 of all three counters. Q0 is already one when TC is one so no need to and it again.
Before the terminal count, both Q0 and TC are zero.
Before the terminal count, at state 0xffe, 4094 decimal, the Q0 (pin 14) of
U1 will be zero, but the Q0 (pin 14) of U3 will have already been one for a while (see above comment).
Inside the '163, TC = T * Q0 * Q1 * Q2 * Q3, so when the counters are cascaded like this with TC connected to T of the next more significant counter, the entire unit works as though you have a single IC that's a 12-bit counter. So, TC of U3 is one only at state 0xfff (decimal 4095).
Q0 will go high first as the terminal count is achieved, then the next clock pulse will cause TC to go high, thus placing a low on the LOAD. The next clock pulse will reload the initial count. Is that correct?
Almost correct.
Code:
Count, U3-14 Q0, U3-15 TC, pins 9 PE/
0xea3 0 0 1 start of the count sequence
0xea4 0 0 1
...etc...
0xeff 0 0 1
0xf00 1 0 1 U3 pin 14 Q0 changes to one
0xf01 1 0 1
...etc...
0xffe 1 0 1
0xfff 1 1 0 U3 pin 15 (TC) to one, PE/ (pins 9) to zero
0xea3 0 0 1 back to the start of the count sequence
I'm a little anxious to try this, thanks for the help, Mike
It looks great and am sure it'll go well.
The simple response:
1. The only necessary change is to connect "J? Clock Output" to U3 pin 14.
2. You can optimize a little by removing the connection between U3 pin 14 and NAND pin 1 but it will still count as intended the way it is.
