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Faulty Intel IUP 201 EPROM programmer

The 74LS374 U38 next to the 8155 is the DAC latch. Bit 5 of the 8155 output port at 03H is wired to the 74LS374 U38 clock input. The firmware first does an output to port 03H with Bit 5 set followed by an output to port 03H with Bit 5 clear to latch a value into 74LS374 U38. Not sure yet if the value latched into 74LS374 U38 comes from other bits in port 03H or somewhere else.

Output port 03H Bit 5 is documented as the DAC CLOCK in figure 10 of Application Note AP-156, but I don't see any other mention of the DAC there.
 
The 8155 RAM-I/O-Timer I/O ports are mapped to I/O address range 00H - 05H. In that range I see the firmware writing to I/O ports 00H, 01H, 03H, 04H, and 05H, but not 02H. In that range I only see it reading from 02H.

Have a look at the datasheet for the Intel P8155 (or its AMD equivalent). This describes the I/O ports in detail. In summary:

Port 00 = Command / Status register
Port 01 = PA, general purpose 8 bit I/O port
Port 02 = PB, general purpose 8 bit I/O port
Port 03 = PC, either general purpose 6 bit I/O port, or control for ports A and B (3 bits each, interrupt, buffer full and strobe)
Port 04 = Timer control, low order byte
Port 05 = Timer control, high order byte

Regards,
John
 
There are two 74LS74 dual D-type flip-flops U23 and U24 next to the 8155. I wonder if those are used to latch the 4 voltage control switch bits that are documented in Figure 10 of Application Note AP-156.

In that case bits 1, 2, 3, and 4 of the 8155 output port 3 would be wired to the D inputs of the two 74LS74, and bit 0 of the 8155 output port 3 would be wired to the clock inputs of the two 74LS74. I'll have to take a look later today and probe those two 74LS74 to see whether or not that guess is correct.

What might be more interesting to find out is what is connected to the inputs of the 8155 input port 2? Bits 0, 1, 2, and 3 are the voltage status bits. The iUP is supposed to turn off a switched voltage supply whenever an overcurrent condition is sensed on a supply line and that is supposed to be reflected in the 8155 input port 2 status bits.
 
Hi,
I've started to trace out parts of the circuit, from the UA723 voltage regulators through to the DAC and associated comparator. Sorry I haven't done enough to answer all the questions raised previously, but here are some pieces of the jigsaw.

TP1 is fed from U1 (UA723). Pin 5 (IN+) is connected to pot R7.

TP2 is fed from U2 (UA723). Pin 5 (IN+) is connected to pot R25.

TP3 is fed from U3 (UA723). Pin 5 (IN+) is connected to pot R32.

On U5 (UA723) pin 5 (IN+) is connected to pot R65, not worked out where output is fed to.

U39 DAC is associated with U41 LM339 (quad comparator).

TP1 is connected to diode CR28
TP2 is connected to CR27
TP3 is connected to CR29
+5V supply is connected to CR30

The cathodes (ie outputs) of these four diodes are connected (ie voltage = to the highest of the inputs minus 0.6V), this feeds into voltage divider made of R108 (2k0 ohm) and R92 (1k0 ohm) to U41 pin 6 (inverting input comparator 2). So with just +5V input to the diodes pin 6 = (5V - 0.6V) / 3 = 1.4V. With TP1/2/3 higher than 5.0V then pin 6 goes proportionally higher.

U41 pin 7 (non-inverting input comparator 2) is fed from U40 741 op-amp which is fed from current output of DAC (U39 pin 4). The output of U41 comparator 2 is pin 1, which is connected to U31 (P8155 I/O chip) pin 33 (PB4) - hence read in software at I/O port 2.

The only other comparator in U41 which appears to be used is #3, so U41 pin 14 (output) is fed to U30 (8085) pin 36, which is RESIN or reset in. I haven't traced the inputs yet, but there is a bunch of resistors and transistors north of U41. Seems rather complicated for a reset circuit?

The U39 DAC is trimmed using R112 (connects to pin 14, Vref+). As gslick wrote the 8 bit binary input to the DAC is U38 74LS374 latch.

I have some hand-drawn sketches of the above, but would like to try and draw them properly. I'm away from the IUP for a few days, I will try and answer some more queries and trace out the other comparator circuit and some of the transistors. The 8085 / RAM / EPROM / TTL glue looks fairly straightforward. However given the interesting stuff is the boundary of analogue and digital this is where I think the problem is.

Regards,
John
 
I've traced out more of the circuit, it certainly is complicated, but there are similar circuits around the U1/U2/U3 regulators.

Here are some further associations between the power supplies, comparators and digit parts of the circuit.

U1 connects to Q2 which also has feed from U32 pin 10 (7407 driver, nb input pin 11 is connected to U24 pin 6, which is 74LS74 output Q1 bar), which drives Q1, Q7 and TP1. Q7 connects to R40 which feeds into U14 pin 6 (-ve input to comparator 2). The output of comparator 2 (pin 2) is fed to U24 (74LS74) pin 13 (CLR2). Output Q2 (pin 9) is connected to U31 pin 31 (8155 PB2).

U2 connects to Q4 which also has feed from U32 pin 12 (7407 driver, nb input pin 13 is connected to U24 pin 8, which is 74LS74 output Q2 bar), which drives Q3, Q8 and TP2. Q8 connects to R41 which feeds into U14 pin 4 (-ve input to comparator 1). The output of comparator 1 (pin 1) is fed to U24 pin 1 CLR1. Output Q1 (pin 5) is connected to U31 pin 32 (8155 PB3).

U3 connects to Q6 which drives Q9, Q11 and TP3. Q6 output connects to Q9 base via R39, Q9 is also driven from U17 pin 1 (MC1489 - not traced further). Q11 connects to R42 which feeds into U14 pin 10 (-ve input to comparator 4). The output of comparator 4 (pin 13) is fed to U25 (74LS74) pin 1 CLR1. Output Q1 (pin 5) is connected to U31 pin 30 (8155 PB1).

On to some further tracing, and some more captures of oscilloscope traces of the comparator outputs.

Regards,
John
 
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Let's see if I transcribed what you said above correctly for the status inputs:
U24 74LS74 pin 5 Q1 -> U31 8155 pin 32 PB3 (+VHIGH)
U24 74LS74 pin 9 Q2 -> U31 8155 pin 31 PB2 (+VLOW)
U25 74LS74 pin 5 Q1 -> U31 8155 pin 30 PB1 (+5.75VSW)

Through elimination that should then leave:
U24 74LS74 pin 9 Q2 -> U31 8155 pin 29 PB0 (-12VSW)

My guess is that both U24 and U25 74LS74 pin 3 CLK1 and pin 11 CLK2 are connected to U31 8155 pin 37 PC0.

And then also guess that the control outputs are:
U31 8155 pin 38 PC1 (-12VSW) -> U25 74LS74 pin 12 D2
U31 8155 pin 39 PC2 (+5.75VSW) -> U25 74LS74 pin 2 D1
U31 8155 pin 1 PC3 (+VLOW) -> U24 74LS74 pin 12 D2
U31 8155 pin 2 PC4 (+VHIGH) -> U24 74LS74 pin 2 D1

Then the firmware turns the switchable voltages on by setting the appropriate U31 8155 PC1, PC2, PC3, and PC4 bits and toggling PC0 to latch the bits into the U24 and U25 74LS74 Q1 and Q2 outputs from the D1 and D2 inputs.

Then the firmware can check the status of the switchable voltage controls from the U24 and U25 74LS74 Q1 and Q2 outputs by reading the U31 8155 PB0, PB1, PB2, and PB3 bits.

And then if an abnormal condition occurs on one or more of the switchable voltages the U24 and U25 74LS74 /CLR1 and/or /CLR2 inputs will be asserted, which then turns off the corresponding D1 and/or D2 outputs.

Does that seem correct?
 
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U41 pin 7 (non-inverting input comparator 2) is fed from U40 741 op-amp which is fed from current output of DAC (U39 pin 4). The output of U41 comparator 2 is pin 1, which is connected to U31 (P8155 I/O chip) pin 33 (PB4) - hence read in software at I/O port 2.

Figure 10 of Application Note AP-156 only documents 8155 bits PB0 - PB3. It says that bits PB4 - PB7 are not used. The document doesn't say anything at all about the DAC, other than documenting 8155 bit PC5 as the DAC clock. Figuring out exactly how the DAC is used is a good mystery to be solved.
 
Through elimination that should then leave:
U24 74LS74 pin 9 Q2 -> U31 8155 pin 29 PB0 (-12VSW)

Yes this is right. Sorry not yet traced any more today. I really need to tidy up my rough hand-drawn schematics, these are just notes really. I have started to use Fritzing but it seems rather rigid (eg have to create R2, R3, R4 and leave unconnected before R5 etc.). But it is free and seems to have no size limits (sure it has really!)

Regards,
John
 
I've finally traced out U24 and U25 (74LS74) and U26 and U32 (7407) so can confirm following

Let's see if I transcribed what you said above correctly for the status inputs:
U24 74LS74 pin 5 Q1 -> U31 8155 pin 32 PB3 (+VHIGH)
U24 74LS74 pin 9 Q2 -> U31 8155 pin 31 PB2 (+VLOW)
U25 74LS74 pin 5 Q1 -> U31 8155 pin 30 PB1 (+5.75VSW)

Yes, except the transistors are driven from Q bar (pin 6 or pin 8 ) not Q (pin 5 or pin 9).

Through elimination that should then leave:
U24 74LS74 pin 9 Q2 -> U31 8155 pin 29 PB0 (-12VSW)

I think you meant U25, pin 8 (Q bar) connects to R75 which drives Q17 and Q19.

My guess is that both U24 and U25 74LS74 pin 3 CLK1 and pin 11 CLK2 are connected to U31 8155 pin 37 PC0.

And then also guess that the control outputs are:
U31 8155 pin 38 PC1 (-12VSW) -> U25 74LS74 pin 12 D2
U31 8155 pin 39 PC2 (+5.75VSW) -> U25 74LS74 pin 2 D1
U31 8155 pin 1 PC3 (+VLOW) -> U24 74LS74 pin 12 D2
U31 8155 pin 2 PC4 (+VHIGH) -> U24 74LS74 pin 2 D1

Yes all correct. Also all the PR (preset inputs) are tied high.

I am making slow progress drawing out the schematic, here's an update (most passive component values not checked - see the photos for resistors):
IUP Sketch draft A_schem.jpg

Next week I hope to fire up the scope again and monitor the comparator outputs during the POST.
Regards,
John
 
I think you meant U25, pin 8 (Q bar) connects to R75 which drives Q17 and Q19.

Yes, the Q1 and Q2 outputs from the two U24 and U25 74LS74 to the U31 8155 PB0 - PB3 inputs are used once each. Easy to make a typo with all of this notation.

If we keep at this eventually we can get the whole thing documented.
 
It looks like I was right them using at least 4 of the transistors
to shut the regulators down. You can see they fed them into the
compensation pins. Not what I expected but still works.
Dwight
 
If I got the part numbers correct here is the list of the ICs on the iUP-201 main board just for reference.

I didn't see a U11 anywhere.

On your iUP-201 unit are all of U19, U20, U21, and U22 populated with P8185 SRAM parts? On my unit only U19 and U20 are populated.

On my unit only U27 (163394-001) and U28 (163395-001) are populated with D2732A EPROM parts. On your unit U27, U28, and U29 are populated.

I'm curious about the purpose of the Up/Down Counters.

Code:
U1  UA723PC     Precision Voltage Regulator
U2  UA723PC     Precision Voltage Regulator
U3  UA723PC     Precision Voltage Regulator
U4  LM339AN     Quad Differential Comparators
U5  UA723PC     Precision Voltage Regulator
----------
U6  74LS244AN   Octal Buffers and Line Drivers With 3-State Outputs
U7  74LS244AN   Octal Buffers and Line Drivers With 3-State Outputs
U8  74LS240PC   Octal Buffers and Line Drivers With 3-State Outputs
U9  D8286       Octal Bus Transceiver
U10 D8286       Octal Bus Transceiver
----------
U12 74LS139PC   Dual 1-of-4 Decoder/Demultiplexer
U13 74LS139PC   Dual 1-of-4 Decoder/Demultiplexer
U14 74LS244AN   Octal Buffers and Line Drivers With 3-State Outputs
U15 74LS244AN   Octal Buffers and Line Drivers With 3-State Outputs
U16 74LS08PC    Quadruple 2-Input Positive-AND Gates
U17 MC1489L     Quadruple Line Receivers
U18 MC1488L     Quadruple Line Drivers
----------
U19 P8185       1KB SRAM
U20 P8185       1KB SRAM
U21
U22
U23 D8282       Octal Latch
U24 74LS74PC    Dual D-Type Positive-Edge-Triggered Flip-Flops with Preset and Clear
U25 74LS74PC    Dual D-Type Positive-Edge-Triggered Flip-Flops with Preset and Clear
U26 7407PC      Hex Buffers with High Voltage Open-Collector Outputs
----------
U27 D2732A      4KB EPROM
U28 D2732A      4KB EPROM
U29 D2732A      4KB EPROM
U30 P8085A      8-Bit Microprocessor
U31 P8155H-2    256-Byte SRAM with I/O Ports and Timer
U32 7407PC      Hex Buffers with High Voltage Open-Collector Outputs
U33 74LS10PC    Triple 3-Input NAND Gate
----------
U34 74LS04PC    Hex Inverters
U35 74LS193PC   Synchronous 4-Bit Up/Down Counters (Dual Clock with Clear)
U36 74LS193PC   Synchronous 4-Bit Up/Down Counters (Dual Clock with Clear)
U37 74LS00N     Quadruple 2-Input Positive-NAND Gates
U38 74LS374N    Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops
U39 MC1408P7    8-Bit Multiplying D/A Converter
U40 UA741TC     Operational Amplifier
U41 LM339AN     Quad Differential Comparators
 
On your iUP-201 unit are all of U19, U20, U21, and U22 populated with P8185 SRAM parts? On my unit only U19 and U20 are populated.

Thanks for the parts list. Yes my IUP-201 has four RAM chips.

I haven't had much time this week to look at the circuit, but I did capture the comparator chip (LM339 - U4 and U41) outputs during the POST.

U4 was easy, on the three comparators used (1, 2 & 4), all of the outputs went straight to 4.0V and stayed there, all the + inputs were higher voltages than the - inputs.

On U41 comparator 2 I used the DSO to capture the comparator 2 output.

Channel 1 - Yellow = Pin 7 (+) , the DAC output
Channel 2 - Green = Pin 6 (-), diode sum output
Channel 3 - Orange = Pin 1 (output)

DSC_0720.jpg

The output was 0 all the time the DAC output was stepping through different levels. Please can gslick run the same check?

Time now to get set for Christmas, so best wishes to all!

Regards,
John
 
For the DAC, you need to look at the output of the opamp.
The output pin of the DAC is a current summing node and
is held at zero by the feedback of the opamp.
I'm a little concerned about the noise on the signals.
Are you using a ground close to the comparator or just the
chasiss?
Dwight
 
I connected the scope probes to an earth test pin near the comparator, and used flying jumper leads from the comparator chip pins to the scope tips, which was probably where the noise came in. I wanted to measure at the comparator inputs rather than the DAC or 741 outputs to ensure I could see the comparator was working correctly (which it is).

Regards,
John
 
The difference I see between your iUP-201 and mine is that with mine during the third step the IN1+ input rises above the IN1- input enough to make the OUT1 output go high again.

The scope probes were connected to U41 LM339AN Quad Differential Comparators
Channel 1 - Yellow = Pin 7 (IN1+) , the DAC output
Channel 2 - Green = Pin 6 (IN1-), diode sum output
Channel 3 - Blue = Pin 1 (OUT1)

I used the same scope settings as you in the first screen capture, except that I set the ground reference 2 division from the bottom instead of at the center. The second screen capture is the same as the first except I changed from 2V to 1V per division.

U41-7-6-1-A.jpg
U41-7-6-1-B.jpg
 
I was wondering, there must be a setup mode for setting the supplies.
If not in software, there might be some locations to set enable
the supplies.
If the noise isn't a factor, it would seem that the supply being measured
at the comparator is over voltage.
The DAC signals look the same but the voltage from the supply is too high.
The first step in the DAC signal looks strange, though. The above/below measurements
look similar so maybe it is not an issue.
I still worry about the noise.
Dwight
 
There is a pair of jumper shunts next to Q20 and Q21. Have you tried to trace how they are connected yet? I wonder if they might have any part of a calibration procedure if they were removed?

The firmware has multiple code paths were the "POWER SUPPLY FAILURE" error message can be displayed. At least 4 or 5. I should spend some time trying to figure out what conditions each path is checking.
 
The difference I see between your iUP-201 and mine is that with mine during the third step the IN1+ input rises above the IN1- input enough to make the OUT1 output go high again.

Thanks for the replies, Christmas is over for another year so had a play today. I tried tweaking R115 to set the DAC output a bit higher to match gslick's trace, the result was now the same as his:

DSC_0724.jpg

and my IUP now passes the diagnostic test! I can't see a fault with the actual power supplies, it just seems to the way the DAC test worked. I think my DAC output had drifted low over the past 25 years, without a service manual very hard to know what the exact settings should be.

I will try an EPROM module tomorrow and program some chips, fingers crossed.

Regards,
John
 
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