Just curious, do you have any interest in trying your Samsung memory without the parity chip? I know we're quite confident at this point that it is just a matter of the chipset not supporting the 1024-row refresh required to properly use 4Mbit DRAM chips... but that parity chip not being a low power module really sticks in my brain.very low profile 9*1Mbit chips with the pin on the backside, so they are only as high as the memory chip length. very tightly packed, siemens/hynix memory.
as for designining your own memory. these are as simple as they can be. just bunch of wires between the pins and chips. i dont know kicad though but it is doable.
now going back to soldering 500 ram chips on sgi o2 memory modules sdz designed recently ... https://sdz-mods.com/index.php/2026/01/15/sgi-o2-128mb-dram-module/
purple ram and anothed dude have 30 pin simms so it is doable
I think it would really help to solidify these findings and to 100% rule out any issues related to refresh intervals.
No pressure, it would just be far quicker and easier for you to pull 4 chips and then test again than it would be for me to desolder 8 L-suffix chips from a donor, desolder the 8 chips currently on my SIPPs, solder the 8 L-suffix chips, test (and likely have it not fix anything), then have to desolder them yet again and then solder the original 256Kbit chips back in.
My brain would love to have closure on this particular aspect if you have time.
Last edited: