HP Logic Analyzers - HP Pre-Processor Modules - HP Inverse Assembler

[gslick]

Did this ever get scanned and posted somewhere?

I'd really like to find the one for the Model 10269B.

I don't have any manuals specific to the 10269B, and haven't found any online anywhere.

I did scan a few more manuals back in July that don't seem to have exact version matches on Bitsavers yet. Looks like I never got around to sending copies to Al. I'll do that now.

10269-90905_10269A_General_Purpose_Interface_Oct83.pdf
10269-90905_10269A_General_Purpose_Interface_Changes_Feb84.pdf
10304-90904_10304B_8085_Inverse_Assembler_Operation_Note_Apr86.pdf
64655A_8085_Interface_Module_Service_Information_64555-90904_Sep87.pdf
64671-90901_64671A_6809-6809E_Interface_Module_Service_Brief_Dec83.pdf

 

[Al Kossow]

Thanks Glen!
I also reorganized the preprocessor directory and moved all 64000-related directories
into test_equipment/hp as I've slowly been moving all of the in-circuit emulator
boxes into test_equipment.

 

[gslick]

Hello, gotcha,

Would you be willing to share your wiring setup for the pods? I'm following the same documentation and troubleshooting a Z80 with my HP1663E and not seeing any opcode fetches; I'm thinking my STAT or CLK wiring might not be correct.

On Pod 1 I have 0-7 as D0-D7, then:

8: /WR (3x through 74LS240)​

9: /IORQ (1x through 74LS240)​

10: /RFSH​

11: /M1​

CLK: /MREQ (1x through 74LS240)​

Pod 2 is all A0-A15 and CLK connected to /IORQ (1x through 74LS240)

Thank you

In case you haven't seen this already, it is possible to use the Z80 inverse assembler without the 74LS240/241 buffers in the 10300B preprocessor by changing the clocking scheme to use Master/Slave clocking and modifying the IA to handle the /WR STAT signal not being inverted.

Some details starting here on this thread:
https://www.eevblog.com/forum/testgear/hp-logic-analyzer-inverse-assemblers/msg5398076/#msg5398076

(gotcha is on that thread, so they have probably already seen that)