RickNel
Veteran Member
I've been trying to revive my IMS 5000SX machine for some months. Finally a local friend has wire-wrapped a replica Front Panel based on the Intersystems design, and it works perfectly with his IMSAI.
But in my 1980 IMS International, this front panel can not read anything from the data lines of the bus. For example, the initial program loader is in EPROM located on the I\O card. When we use the Front Panel to run or step the system, we can see (by data probing the I\O card) that EPROM is enabling and sending data out through the I\O card's bus driver chips, but the CPU card does not read anything off the bus.
I believe the issue is that my CPU card is hard-wired so that it will only read data when the RUN line (bus pin 71) is under the control of the Z80 CPU. When the RUN signal is coming from the Front Panel, through a header on the CPU card that is in parallel with the Z80, data input is blocked.
I have all the original documentation and schematics, and it seems that the system was supposed to be able to work with a front panel, although not shipping with one. It has a jumper to put mWrite signal on bus pin 68 for Front Panel use - but we can't see how to work a round this issue with the Run signal.
Has anyone seen or sorted this kind of problem before? Any pointers greatly appreciated. I can make any documentation available if that would be of interest, but did not want to clutter the forum with attachments to this exploratory appeal.
Thanks to any or all,
Rick
But in my 1980 IMS International, this front panel can not read anything from the data lines of the bus. For example, the initial program loader is in EPROM located on the I\O card. When we use the Front Panel to run or step the system, we can see (by data probing the I\O card) that EPROM is enabling and sending data out through the I\O card's bus driver chips, but the CPU card does not read anything off the bus.
I believe the issue is that my CPU card is hard-wired so that it will only read data when the RUN line (bus pin 71) is under the control of the Z80 CPU. When the RUN signal is coming from the Front Panel, through a header on the CPU card that is in parallel with the Z80, data input is blocked.
I have all the original documentation and schematics, and it seems that the system was supposed to be able to work with a front panel, although not shipping with one. It has a jumper to put mWrite signal on bus pin 68 for Front Panel use - but we can't see how to work a round this issue with the Run signal.
Has anyone seen or sorted this kind of problem before? Any pointers greatly appreciated. I can make any documentation available if that would be of interest, but did not want to clutter the forum with attachments to this exploratory appeal.
Thanks to any or all,
Rick