PhilipA
Veteran Member
A little more data: A52 and A61 video linearizer roms (1024 x 4 bit)
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Lanier Model 103 "No Problem" word processor
- Thread starter PhilipA
- Start date
PhilipA
Veteran Member
Took look at the bus on the printer, overlapping and corrupt levels.
Removed the tri-state buffers from the board- ordered some dip sockets, forgot I didn't have any 16 pin ones left.
Removed the interface latch buffers also, got sockets for these.
Inter chipset communication is good and sane. This will at least allow me to try and isolate what's overlapping signals onto the bus.
Phil
Removed the tri-state buffers from the board- ordered some dip sockets, forgot I didn't have any 16 pin ones left.
Removed the interface latch buffers also, got sockets for these.
Inter chipset communication is good and sane. This will at least allow me to try and isolate what's overlapping signals onto the bus.
Phil
PhilipA
Veteran Member
With nothing connected, the i/o bus just strobes steadily.
Plugging in the external i/o latch buffers didn't do too much, changed some pulse timings but overall didn't cause anything that I would say looks like a distressed signal.
Adding the tri-state buffers back in results in some of the bus going to weird timing and resulting in two signals being interposed at the same time, giving an odd third state, yes no and maybe.
Traced back through and socketed the i/o enable circuit path. There's a 7404 in there and I've had those go bad before. Bad weather causing the power to be unreliable tonight so tomorrow I'll take a look at that circuit.
Phil
Plugging in the external i/o latch buffers didn't do too much, changed some pulse timings but overall didn't cause anything that I would say looks like a distressed signal.
Adding the tri-state buffers back in results in some of the bus going to weird timing and resulting in two signals being interposed at the same time, giving an odd third state, yes no and maybe.
Traced back through and socketed the i/o enable circuit path. There's a 7404 in there and I've had those go bad before. Bad weather causing the power to be unreliable tonight so tomorrow I'll take a look at that circuit.
Phil
PhilipA
Veteran Member
Tested every chip that I pulled off and they all work as per datasheet.
PhilipA
Veteran Member
I'll just leave this here.
Yup, that's CP/M.
Yup, that's CP/M.
PhilipA
Veteran Member
For the record, if anyone needs the software the aes images are on Archive.org and can be written using a Greasweazle or any other flux imaging hardware. Once a few bugs are worked out Peter said he would post the CP/M images on GitHub (I cannot claim fame on the creation of this diskette and the work that's gone into creating the CP/M BIOS for this machine).
It's also far too interesting to scrap.
Phil
It's also far too interesting to scrap.
Phil
PhilipA
Veteran Member
Requesting interrupts before the controller was initialized... That caused some curious behavior on cold boot!
Floppy controller doesn't have an internal drive spindle motor timeout so that needs to be baby-sat in code.
Ultimately, the disk magnetic flux format was determined, the data arrangement was decoded and the 8080 code was disassembled from the original AES operating system (which is not cp/m as thought, but a multi-tasking os that is really quite clever given the hardware) but picking that apart allowed the basic memory layout, internal i/o to be reverse engineered for video output, disk access, keyboard handling etc., which meant that then the entire machine can be emulated as it is a known architecture; within that emulation a BIOS can be written and a bootloader that kicks out of the AES boot ROM (the first 512 bytes of RAM are mapped to the boot ROM on cold boot, which loads from disk the first code on the disk to a known memory location- that bootloader code can then run, disable the boot ROM and copy the required BIOS code for CP/M to the low memory and then boot up into CP/M from the floppy.
It's a very raw hardware, with no inbuilt protection or error checking. That's all handled in software, and with 32k of RAM it is hard to catch all that; the disk format with odd bytes per sector means it doesn't jive too well with the way CP/M expects the sector format so there's a lot of lost space on a CP/M formatted disk.
Is what it is though, and the fact the first disk image created halfway around the globe on an emulated copy of the hardware booted first time is frankly amazing.
Floppy controller doesn't have an internal drive spindle motor timeout so that needs to be baby-sat in code.
Ultimately, the disk magnetic flux format was determined, the data arrangement was decoded and the 8080 code was disassembled from the original AES operating system (which is not cp/m as thought, but a multi-tasking os that is really quite clever given the hardware) but picking that apart allowed the basic memory layout, internal i/o to be reverse engineered for video output, disk access, keyboard handling etc., which meant that then the entire machine can be emulated as it is a known architecture; within that emulation a BIOS can be written and a bootloader that kicks out of the AES boot ROM (the first 512 bytes of RAM are mapped to the boot ROM on cold boot, which loads from disk the first code on the disk to a known memory location- that bootloader code can then run, disable the boot ROM and copy the required BIOS code for CP/M to the low memory and then boot up into CP/M from the floppy.
It's a very raw hardware, with no inbuilt protection or error checking. That's all handled in software, and with 32k of RAM it is hard to catch all that; the disk format with odd bytes per sector means it doesn't jive too well with the way CP/M expects the sector format so there's a lot of lost space on a CP/M formatted disk.
Is what it is though, and the fact the first disk image created halfway around the globe on an emulated copy of the hardware booted first time is frankly amazing.
Hi everyone, so yeah I got sucked into a very deep rabbit hole with the 103. Phil already explained how we got to the point were CP/M is running, I just wanted to add that without the service manual from daverand it would have been much more difficult if not impossible.
I am documenting everything we learned about the machine and will put it all up on Github after the last kinks have been worked out.
I am documenting everything we learned about the machine and will put it all up on Github after the last kinks have been worked out.