I ran across a couple things in the schematic that are curious to me. Maybe someone here knows what's happening.
1) In the schematic, the port address decoder is not connected to ISA bus address line A2. This suggests the first parallel port is available at 0x378 (and 0x379, 0x37A) but doesn't that also mean the port is mirrored at 0x37C (and 0x37D, 0x37E)?
2) I noticed on the Init line to the printer, coming out of the 74LS174 flip flop is a cascade if two inverters. Why invert then invert? The only reason I can think of is to add a tiny timing delay to the Init signal. Is that the case?