ok, Took a look at that timing diagram in the manual. Your're not going to like what I found. But that timing diagram is a very rough estimation. It's not the first time I found a 40yr old typo in a manual [or software]. Basically I measured the read timing cycle with a ruler and then calculated the timing marks from the ratios. Below is all of the measurements.
Actually I'm missing the part. They had to pull the paper order for me from PT to look up the specs. It was a special order back in the day for PT according to them. It was never an off the shelf part. I think that is why many 48kra are no longer around. If the delay went so did the card.
If they pulled the specs off the PT order, can they share it with us. I mean are they withholding this information unless we buy it ?
I was looking at part 3D7220-50 which is 14 pin and should be easy to make an adapter. I'm going to see if they have any at surplus stores next week. The only place I found with them had a 10 unit minimum order. I'd get that many as a "life time supply" if I knew they would work.
oh ok, cool
Which place is this ? I wonder if I have them on my list too.
As for the adapter you might want to use one of the old style 16pin DIP breadboards - the kind with the little u-shaped pins which hold the component leads [I have a pic around here somewhere] - fold the pins on the IC, hot glue it on there, and wire the pins to match the connections on the circuit board for U50. I think it will still have a low profile to fit in the S-100 slot.
I guess I won't know till I try. Also yes, the 320 is not a typo. If you look at the 48kra timing diagram, while not easy to measure exact timing from, you can see tap 4 and 5 are almost on each other in timing. I should also ask data delay about the units in my early 16kra and 32kra. Maybe they are close to the 48kra. If they are I guess I could use 10 of the known to work spec ones because I have 4 16kra cards and one 32kra. Good to have spare parts.
yes, I also see that Tap4 and Tap5 are very close, I show this below in the measurements. I haven't looked closely at the Timing cycles on the 16KRA just yet.
I'll take a look at the maxim parts as well later. I didn't follow your link yet.
Cheers,
Corey
Timing Diagram Measurements:
I scaled the page with the read timing cycle to 6in length, for 489nsec, between the start timing mark and the end timing mark
So for the read timing cycle; 6in = 489 nsec
The Timing marks for the Phase2 clock at the top for 210ns and 289ns are what's already messed up.
From measuring these timing marks, I get the actual time.
I'm only using 1/16th of an inch for the resolution - 1/16th inch = 5nsec
And I get a discrepancy already from using their timing marks.
The Timing diagram is not much help if they can't draw it correctly.
Phase2(210ns) = 2.75in ; actual time = 224.1ns (+14ns)
Phase2(289ns) = 3.625in ; actual time = 295.4ns (+6.4ns)
The Delay Line is fed with signal CAE, so as the input, this can be considered Tap0 with respect to the start of the read timing cycle. And the delay time for CAE on the JK flip-flop from Phase2 clock is rather long, 40.7nsec, for a Schottky TTL part (U49). It's not outrageous, but something else to verify. Q5 may still have some significant delay even though it's wired as a current buffer.
Measuring from the start timing mark in the read cycle, these are the timing values.
Tap0: 0.5in = 40.7ns
Tap1: 1.1875in = 96.7ns--------> +56ns
Tap2: 1.75in = 142.6ns-------> +50ns
Tap3: 2.1875in = 178.2ns-------> +35ns
Tap4: 4.25in = 346.3ns-------> +168ns
Tap5: 4.3125in = 351.4ns-------> +5ns <-----very short, about the same as a delay on a logic gate
Suffice it to say we should really borrow the actual part from someone who has a working 48KRA and take actual measurements. Because the timing marks on that diagram indicates a very unique delay line. It would help if we can verify this ourselves. Because, as it stands right now, that one part you mentioned and the one I mentioned won't work in here.
All you need is the part, not the whole board, just pop it in a breadboard. Add power, pump it with a oscillator, which is not faster than the delay timing, so for this - nothing faster than say 1Mhz, just to make it easy. Then just measure the delay taps with a o'scope, putting the first scope probe on the oscillator output, with the trigger set to chan.1. Then take the 2nd probe on chan.2 and measure the delay on each tap. If you have a decent o'scope, it should have onscreen cursors to measure the delay time. That's the proper way to get this done unless that company can provide us with a real datasheet. I can do this with work with my delay line, since the 16KRA has a different part#, we might as well get it recorded before they all go bad.
Which part is on the 32KRA again ? same at the 48KRA or the 16KRA ?
And after that is all done, it would be really nice to make a printout of the actual timing diagram using a Logic Analyzer to use as reference.
Dan