Olivetti M40 / M44 L1 boot disk

[gferluga]

Does anyone have the Olivetti M40 or M44 L1 boot disks ?
There is a bios configuration in Mame so I'm assuming someone test it.
Thanks in advance.

 

[Xolod]

Try this.. https://mega.nz/file/bhoBBA4C#zXfdfvsURAy6KvGnXnNTB_-EIABtUmraAHtFE-3EGw8

 

[ldkraemer]

I had a look at the *.SCP files and the HxC Software shows them ALL corrupt.

THANKS.

Larry

 

[ldkraemer]

Here is what the HxC Software displays:

See attached PNG files.

Larry

 

[tpaxia]

Does anyone have the Olivetti M40 or M44 L1 boot disks ?
There is a bios configuration in Mame so I'm assuming someone test it.
Thanks in advance.

The m30 and m40 in mame are shells, most of the hardware is missing and the z8001 there has plenty of bugs!

 

[Xolod]

I was gathering information about the Olivetti L1 M44 here, but unfortunately, the developers of MAME weren't particularly interested.

https://forums.bannister.org/ubbthreads.php?ubb=showflat&Main=9530&Number=122484#Post122484

 

[tpaxia]

I was gathering information about the Olivetti L1 M44 here, but unfortunately, the developers of MAME weren't particularly interested.

https://forums.bannister.org/ubbthreads.php?ubb=showflat&Main=9530&Number=122484#Post122484

Yes, I saw it, I wanted to work on a M30/M40 emulator for a long time. The boot floppies you provided help,
I can try to add support to MAME with a little more hardware info...
The Z8010 is already present in an old P8000 port so it should be quite easy to fix and incorporate.

I built an harness to test the Z8000 and developed a soft core. I currently have ~2900 validated instruction tests.
I then fixed 26 distinct Z8000 instructions across ~57 opcode-handler variants in MAME.
They are grouped into 13 root-cause bugs plus the addr_to_reg segmented-addressing helper.
The harness also works as a fully functional M20, I think I still have enough space in the FPGA to implement the missing M30
hardware.


--------------------------------------------------------------------------------
BUGS BY ROOT CAUSE
--------------------------------------------------------------------------------

[A] Shift/rotate V (overflow) flag wrong Handlers: 23
Root cause: V derived by comparing only final vs. original sign bit (wrong
for 2-step/multi-bit shifts); logical shifts computed no V at all
(CLR_CZS). Now accumulated per shift step.
Instructions: RL, RLC, RR, RRC, SDA, SDL, SLA, SLL, SRL (B/W/L forms)

MULTL/DIVL 64-bit word order on little-endian Handlers: 10
Root cause: RQ() quad accessor has swapped word order on LE host; operand
read from wrong half and result stored wrong. Now uses explicit RL()
high:low pairs.
Instructions: MULTL, DIVL

[C] MULTL multiplicand from wrong pair Handlers: (subset of B)
Root cause: Read multiplicand from dst[63:32] instead of the low pair
dst[31:0].
Instructions: MULTL

[D] DIVW/DIVL overflow CASE 4 quotient discarded Handlers: 1 (+DIVL in B)
Root cause: On the representable-overflow case it forced the result to
-1/0, destroying the low quotient bits the hardware leaves in the register;
DIVL also took Z/S from the wrong value.
Instructions: DIVW, DIVL

[E] MULT carry boundary off-by-one Handlers: 1
Root cause: Used -0x7fff/0x7fff instead of -0x8000/0x8000 for the C flag.
Instructions: MULT (MULTW)

[F] COMFLG didn't toggle H Handlers: 1
Root cause: Complemented C/Z/S/PV but not H; hardware XORs H too.
Instructions: COMFLG

[G] POPL @Rd,@Rs wrote to register Handlers: 1
Root cause: Destination is indirect (memory) but code did RL(dst)=...;
now WRIR_L.
Instructions: POPL

[H] EXTSL wrong quad word order Handlers: 1
Root cause: Sign-extend long->quad used RQ(); now writes RL(dst) from sign
of RL(dst+2).
Instructions: EXTSL

Dynamic-shift dispatch/count Handlers: 3
Root cause: Byte dynamic shift called static SRLB instead of SDLB;
SDLL/SDAL masked the shift count & 0xff instead of treating it as signed
int8 (broke negative/right shifts).
Instructions: SDLB, SDLL, SDAL

[J] Translate block wrote RH1 too early Handlers: 8
Root cause: TRIB/TRTIB/TRDB/TRTDB (+ memory/repeat variants) loaded RH1
before the address-register update, corrupting the pointer. Deferred
RB(1)=xlt to last.
Instructions: TRIB, TRTIB, TRDB, TRTDB

[K] Compare-string Z flag / CPSIR repeat Handlers: 5
Root cause: CPS byte/word set only V on count exhaustion; hardware also
sets/clears Z. One compare-string-repeat handler had bogus repeat/Z logic
removed.
Instructions: CPSIB, CPSDB, CPSIW, CPSDW

[L] RLDB/RRDB nibble-digit rotate Handlers: 2
Root cause: Temp saved the wrong register (RB(b) vs RB(a)); S flag never
set and Z computed on the wrong basis.
Instructions: RLDB, RRDB

[M] addr_to_reg segment mask Handlers: 1 helper
Root cause: Segmented address writeback preserved bit 15 and only 7 segment
bits (0x80ff/0x7f00) instead of the full high byte (0x00ff/0xff00).
Instructions: segmented address-register writeback (LDA/LDAR, seg auto-inc/dec)

 

[Xolod]

I'm really pleased with your post!!! I'm glad someone decided to make an M44 emulator, and on FPGA at that!!! I'm also dabbling in Verilog. Tell me more about what you've already accomplished.

 

[AndrewMag]

Hello everyone.
Given the interest in the Olivetti "Linea 1 (L1)" M30/M40 systems (and I guess also for the updated M34/M44 versions), I’d like to join this fascinating discussion.

I should start by saying I don't have the expertise to create a hardware or software emulation of these machines, but I do own a complete L1 M40 that I am beginning to restore, along with a set of boards to upgrade it to an M44.

In my opinion, the real problem with these machines is the scarcity of available software documentation, even though a vast amount was produced back in the day. From what I’ve gathered, when the system was launched, it was essentially split into two sub-versions for different markets: the ST (scientific) and the BC (business).

The main difference between them was the software. Initially, Olivetti released operating systems for these machines that emulated the old "CPU19"—a CPU built on two PCBs using entirely TTL logic for the TC800, P6060, and BCS3030 systems. Consequently, the "ST" version featured the "ESE" (Extended System Environment)—virtually identical to that of the P6060 and P6066 to facilitate software migration—while the "BC" version ran "DOS" (which, of course, has nothing to do with Microsoft's DOS :D), a system very similar to the OSs used on the TC800 and BCS3030. Later, the BC version was also equipped with another operating system, BCOS II; while partly derived from earlier systems, it was essentially new. It appears to have been quite successful—in fact, my M40 seems to have this installed on its ST-506 hard drive. Shortly thereafter, the true L1 operating system, MOS, was released; it was far more powerful and capable of handling multiple languages, such as FORTRAN, Pascal, COBOL, and so on.

The aim here was essentially to provide an overview of the operating systems used by these computers. As I mentioned, there is very little documentation available for 2026 systems, so I would ask anyone who has any to share it, if possible.

At the end of this message, I am providing a link to my Drive folder containing the floppy disk images I have collected; I haven't tested them yet (as I have yet to restore the hardware).

I am particularly interested in finding as much information or as many floppy images as possible for the ESE environment. I noticed photos of manuals in some of the earlier MEGA links, and I would like to ask if it might be possible to have them scanned—thanks!

[SEE HERE FOR LINKS]

 

[bsdphk]

In Datamuseum.dk we have a L1/M55: https://datamuseum.dk/wiki/Genstand:11003147

We have no (catalogued) software, data-media or documentation for it, but there are still boxes from that donation which have not be examined in detail.

I mid 1980ies Olivetti signed a huge contract, (DKR 750M, likely the largest IT contract in Denmark at the time), to onlike all savings banks & credit unions in Denmark.
We know this computer is related to that project, but not precisely how, but we have a fair amount of documentation of the "TP1/TP2/TP2½" projects.

I have only examined the machine superficially, to determine if there were any data-media to preserve, and I seem to recall that I concluded that the CPU was a Z8000.

 

[Xolod]

Yes, I'll scan all the documentation available to me. I also ask you to take photos of your computers and boards. And perhaps you can make ROM dumps or at least check your versions.

 

[tpaxia]

I'm really pleased with your post!!! I'm glad someone decided to make an M44 emulator, and on FPGA at that!!! I'm also dabbling in Verilog. Tell me more about what you've already accomplished.

What would you like to know? I gave a talk about my (AI accelerated!) M20/Z8001 efforts at vcfed east 2026:

retro_z8000

Retrocomputing in the Age of AI Rebuilding a forgotten 16-bit ecosystem from a box of floppies to complete hardware recreation with modern FPGA tools and AI-assisted development Salvatore Paxia tpaxia@gmail.com VCFED East 2026

docs.google.com

I don't know which L1 mini we'll be able to reproduce but at least an M30/M40 with floppy, HD and a terminal seems possible.

 

[tpaxia]

Hello everyone.
Given the interest in the Olivetti "Linea 1 (L1)" M30/M40 systems (and I guess also for the updated M34/M44 versions), I’d like to join this fascinating discussion.

I should start by saying I don't have the expertise to create a hardware or software emulation of these machines, but I do own a complete L1 M40 that I am beginning to restore, along with a set of boards to upgrade it to an M44.

In my opinion, the real problem with these machines is the scarcity of available software documentation, even though a vast amount was produced back in the day. From what I’ve gathered, when the system was launched, it was essentially split into two sub-versions for different markets: the ST (scientific) and the BC (business).

The main difference between them was the software. Initially, Olivetti released operating systems for these machines that emulated the old "CPU19"—a CPU built on two PCBs using entirely TTL logic for the TC800, P6060, and BCS3030 systems. Consequently, the "ST" version featured the "ESE" (Extended System Environment)—virtually identical to that of the P6060 and P6066 to facilitate software migration—while the "BC" version ran "DOS" (which, of course, has nothing to do with Microsoft's DOS :D), a system very similar to the OSs used on the TC800 and BCS3030. Later, the BC version was also equipped with another operating system, BCOS II; while partly derived from earlier systems, it was essentially new. It appears to have been quite successful—in fact, my M40 seems to have this installed on its ST-506 hard drive. Shortly thereafter, the true L1 operating system, MOS, was released; it was far more powerful and capable of handling multiple languages, such as FORTRAN, Pascal, COBOL, and so on.

The aim here was essentially to provide an overview of the operating systems used by these computers. As I mentioned, there is very little documentation available for 2026 systems, so I would ask anyone who has any to share it, if possible.

At the end of this message, I am providing a link to my Drive folder containing the floppy disk images I have collected; I haven't tested them yet (as I have yet to restore the hardware).

I am particularly interested in finding as much information or as many floppy images as possible for the ESE environment. I noticed photos of manuals in some of the earlier MEGA links, and I would like to ask if it might be possible to have them scanned—thanks!

Google Drive: Sign-in

Access Google Drive with a Google account (for personal use) or Google Workspace account (for business use).

drive.google.com

Google Drive: Sign-in

Access Google Drive with a Google account (for personal use) or Google Workspace account (for business use).

drive.google.com

That's an amazing collection, thanks!

 

[gferluga]

Back in 1986, my first summer job was as a COBOL developer on Olivetti M40 systems in Italy. That was exactly 40 years ago, and unfortunately I don’t remember much about that experience. I no longer have any documentation or source code from those projects.

Fortunately, the lead programmer I worked with is still alive (he’s now 71), and I’m going to try to get in touch with him. He may still remember some interesting details.

Around the same time, Poste Italiane made a massive investment in the Olivetti Linea 1 platform (M30/M40/M44/M54). My father was a manager at Poste Italiane and was directly involved in several of those implementation projects. This excellent article (in Italian) provides a fascinating overview of that period. If you use an automatic translator, it’s well worth the read:

Così sono state informatizzate le Poste tra gli anni ’80 e ’90

Salvatore Luongo, racconta la grandiosa avventura che ha portato alla realizzazione di un’unica rete per tutte le strutture aziendali di Poste.

tgposte.poste.it

 

[AndrewMag]

Good evening everyone. Just a quick update: I have gathered all the material in my possession (manuals, photos, and floppy disk images) into a new single Google Drive folder. I must give special thanks to Stefano Marinelli, a former field technician for the Olivetti L1 who is now retired and has several of these working machines in his collection.

Olivetti L1 M40 - Google Drive

drive.google.com

 

[tpaxia]

Good evening everyone. Just a quick update: I have gathered all the material in my possession (manuals, photos, and floppy disk images) into a new single Google Drive folder. I must give special thanks to Stefano Marinelli, a former field technician for the Olivetti L1 who is now retired and has several of these working machines in his collection.

Olivetti L1 M40 - Google Drive

drive.google.com

Thanks! I know nothing about the M30/M40s but the manuals (especially the diagnostics) are very informative.
I think we should be able to quickly put together in MAME at least the CPU+RAM+console which works until the IPL.
The floppy controller is also looking quite promising.

I put the info i gathered so far (mostly from reverse engineering the ROM) here:

GitHub - tpaxia/l1_m40: Olivetti M30/M40 (L1) boot-ROM reverse-engineering & MAME bring-up — documentation

Olivetti M30/M40 (L1) boot-ROM reverse-engineering & MAME bring-up — documentation - tpaxia/l1_m40

github.com

It would be great if somewhere we could find the description of the device at 0xFF80..0xFF8F and 0xFF41 bit map (READY/NMI control?)

If the M30/M40 experts find anything stupid...please let me know.

 

[Xolod]

You've done a tremendous job, and I hope you'll publish your results. I'm particularly interested in the FPGA part, as well as automated testing on the FPGA and the software emulator, and comparing the results.

Here https://misterfpga.org/viewtopic.php?t=10523 someone writes that they're also working on the Z8000.

 

[tpaxia]

You've done a tremendous job, and I hope you'll publish your results. I'm particularly interested in the FPGA part, as well as automated testing on the FPGA and the software emulator, and comparing the results.

Here https://misterfpga.org/viewtopic.php?t=10523 someone writes that they're also working on the Z8000.

Without claude it would have taken me 2 years to clone the cpu!
I am slowly making the repositories public. Here is the testing part.

https://github.com/tpaxia/z8000_test

The software emulator (I'll backport to MAME the z8000 fixes) has been public for a bit.

 

[tpaxia]

Good evening everyone. Just a quick update: I have gathered all the material in my possession (manuals, photos, and floppy disk images) into a new single Google Drive folder. I must give special thanks to Stefano Marinelli, a former field technician for the Olivetti L1 who is now retired and has several of these working machines in his collection.

Olivetti L1 M40 - Google Drive

drive.google.com

Any chance you could dump a character generator rom from a video card? Maybe also take a picture of your board with the
GO number? I saw a picture of the GO252 and I am emulating that. The rom there seems to be the GI 9428DS-2067.

I think I made good progress: MMU, memory, diagnostic display, cpu, arbiter, device enumeration and video all work. Floppy almost done.
Next I plan to boot the diagnostics which will give us more detailed info about the hardware.

Is this the expected screen? The font is temporary.




[M40 console] code = 0x01 (1)
[M40 console] code = 0x02 (2)
[M40 console] code = 0x44 (68)
[M40 console] code = 0x55 (85)
[M40 console] code = 0x28 (40)

 

[AndrewMag]

Thanks a lot! You are doing truly commendable work—kudos!
The startup screen looks correct to me. At this YouTube link, you can watch the full hard disk boot sequence of an M30 running BCOS II.

As for the ROMs, I’ll do my best to dump them—perhaps next week before I go on vacation.

Also next week, I should have the schematics for the UC042 (CPU) and GO252 (trivalent alphanumeric video) boards in hand.

You can find photos of the GO252 and the GO255/A graphics extension in the Google Drive folder I already shared.
Specifically, my M40 has two of these boards installed: one from 1985 and the other from 1986.

I’ll take this opportunity to provide a complete list of the boards I have:
- GO151 RS232 and current loop interface
- GO252 B/W alphanumeric KDC controller
- GO201B STC 20MB formatter controller
- GO200X STC 20MB controller
- GO363 ST506 interface controller (XU1707/9)
- GO252 B/W alphanumeric KDC controller
- RA57C 1.0 MB RAM
- UC042 Central Unit (M30/40)
Spare parts/extras:
- (2x) GO280B floppy/minifloppy controller
- GO327 RS232 and current loop interface
- GO255/A graphics video extension
- RA57A 2.0 MB RAM
- UC048 Central Unit (M34/44)

If anyone reading this message has a spare monitor to sell or trade, please feel free to contact me privately; I currently have only one, and I would love to get my M40 up and running again with a dual-monitor setup, just like it was over forty years ago.