It's not in my experience/knowledge.
But I can say that in practice, strictly meeting the 15 us requirement may not be an issue. For example, about half an hour ago, I brought out an IBM 5150 motherboard. No expansion cards apart from a video card, thus, it would always boot into Cassette BASIC. In BASIC, I then performed the following procedure MANY times, using different test periods in step 4.
Step 1: Write the byte of 66h into address 40h. [DEF SEG=&H40 followed by POKE 0,66]
Step 2: Read back the contents of address 40h to verify that the write took. [PRINT PEEK(0)]
Step 3: Disable DMA based RAM refresh, which for the IBM 5150 (not the 5160), I did by grounding pin 13 of the motherboard's 8253 chip.
Step 4: Wait for the test period to pass, doing nothing in that time.
Step 5: Enable DMA based RAM refresh (by undoing step 3).
Step 6: Read back the contents of address 40h to see if still holds 66h.
( In step 4, do nothing. For example, a read of address 40h in that period would compromise the test, because a read of address 40h would 'manually' refresh the RAM rows associated with address 40h. )
Every time that I used a test period of 5 seconds, I then, at step 6, successfully read back 66h.
Almost every time that I used a test period of 15 seconds, step 6 resulted in the screen clearing then PARITY CHECK 1 appearing.
So, the TMS4164-20 RAM chips used in bank 0 of my 5150 motherboard, can, without refresh, reliably (within the context of the experiment) hold their contents for 5 seconds. The TMS4164-20 datasheet [
here] indicates that all 256 rows be refreshed within 4 ms (i.e. an inter-row period of about 15 us). This is like a factor of a thousand, 4 ms versus 5 seconds.
I have seen similar performance from other dynamic RAM chips of the period.
All of the data sheets show the same refresh requirement. It's as if JEDEC, years prior, to create standardisation/competition, defined a 'baseline' refresh requirement which all manufacturers of dynamic RAM of the era had to put into their data sheets, even though in practice, many chips very greatly exceed the spec.
But maybe there are some make-model of dynamic RAM chips used in the IBM 5150 (and clones) that have a refresh requirement that is close to what is in the data sheet.