Apollo Guidance Computer - AGC.
I don't want to hijack Marty's 11/45 thread - but for a bit of light relief from PDP-11's...
I have always been interested in the Apollo moon landings ever since I was a youngster back in 1969 - being woken by my father and wrapped in a blanket so we could watch the moon landings live on some grainy black and white TV at some unearthly hour of the morning (if I remember correctly).
So, my interest was woken many years later when I came across this website
http://www.ibiblio.org/apollo/ containing a software emulator of the AGC complete with the actual software for the command module (Colossus) and Lunar Lander (Luminary) that had been reconstructed from old listings.
The schematics are also online at
http://klabs.org/history/ech/agc_schematics/.
I was looking for an 'excuse' to learn VHDL for programming FPGA's (up until that point I had been using schematic capture) so I decided to try and implement the AGC on an FPGA. Sounds simple - bad move! The AGC is basically combinatorial logic with the registers, counters etc. arranged as cross-coupled 3-input NOR gates. This works find if you are using basic NOR gates - but bring it anywhere near an FPGA (which is a sequential logic device) and you get problems. So, after many false starts and long nights toiling away with large drawings and EXCEL, I managed to succeed in getting a hardware implementation that worked and would run Colossus, Luminary and the AGC equivalent of the MAINDECS. Whether it does really work or not - we haven't yet found out as we haven't built a rocket large enough to test it out!!!
Interestingly, when I ran the AGC equivalent of the MAINDECS, I was getting errors. After a few e-mails to the software emulator author - we pin-pointed some deviations in the software emulation from the real hardware. The MAINDECs had been modified by the author to run with the software emulator (on the assumption they were in error). Interestingly, when I reverted the code back to what it was, it passed muster on my FPGA. So, I am fairly confident my FPGA implementation is pretty accurate.
Version 1 of the VHDL code can be found at
http://opencores.org/project,agcnorm. There is a version 2 that I haven't published yet (I found a couple of areas where multiple inverters were connected in series to apply delays to certain clock signals).
You need a logon to opencores - but if anyone wants a copy I am quite happy to provide you with one directly. Just send me a PM.
OK - enough foolishness - back to Marty's 11/45...
Interesting about the PSW on a hard reset. I must admit - my train of thought was "this is how it must work so that must be what DEC did". However, when you actually check the schematics - it sets the PSW to 0 (and this is clearly not a documentation error as we have two 11-45's that actually do it!).
We are all 'fools' here - but trying to gain knowledge by learning together. Sure, we will make mistakes, go off the beaten track, get lost etc. etc. etc. but in the end we will get a few 11/45's back to health and learn an awful lot in the process. As with Marty's PDP-8 thread - there will be enough information in these threads on the 11/45 to write an entire book with...
Marty: If you want to see the (beta) VHDL for an 11/70 have a look at
http://opencores.org/project,w11.
Dave