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Sphere-1 Replica Project

falter

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The Sol prototype PCB replica is pretty much done, the JOLT replica is on its way to production, so for my next project, I have decided to tackle something much more difficult, the Sphere-1. I'm starting with their CPU/2 board, which thanks to bzotto we have excellent scans of to work with. I've already corrected and aligned the scans of both sides to get going.

A fellow named Andrew Shapton has already started a project to replicate the Sphere-1 CPU board and may in fact already be done.. I'm not sure. He has a github for it. His seems to take a more modern rearrangement, whereas mine aims to be a visually accurate replica of the original.

The challenge with this one is obviously nobody so far has produced photos of an unbuilt board or the original artwork. All photos of the Sphere boards have components installed on one side, which obscures certain tracks from view. Thanks to Ben's amazing curation of Sphere stuff, we do have a schematic, so I'm hopeful the board will tend to work out the way it's supposed to if that is accurate. Another problem - I still don't have a way to program 1702as to burn the PDS firmware.

Going to be a long haul for sure, but I have blind confidence! Right now I've just got the footprints placed and a few tracks to satisfy my ADD.
 

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Question - I've always wondered on older boards what these 'dogbones' between IC pin pads are? Is it a way to prevent accidental solder bridges or something? Sphere seems to have been a huge fan of these. And not using the same via size twice...

dogbone.png
 
Question - I've always wondered on older boards what these 'dogbones' between IC pin pads are? Is it a way to prevent accidental solder bridges or something? Sphere seems to have been a huge fan of these. And not using the same via size twice...
Unless they are covered by resist IMO they'd *encourage* bridges. They look to me like parts of a standard IC footprint tape-decal that pre-positions traces between IC pins to ensure accurate spacing, then one uses them (e.g., between pins 1 and 2) or not when taping out the circuit.
 
Yes, there was a standard dual in line footprint that also contained track 'stubs' between the pins.

After completing the layout, you could have scraped the unused stubs off with a scalpel. But that was more work...

I still have some somewhere in my box of PCB stuff.

Dave
 
Just pulled my old box of PCB transfers out - and the first packet I opened had some DIL transfers with "dog bones".

Dave
 
I bought a bunch of Bishop graphics PCB layout stuff, just to have historical examples.

Is it true they used to call some of the shapes 'puppies' or 'dolls'?
 

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So this is how I'm planning to tackle the front side of the CPU board, which regrettably has no surviving artwork or photos that aren't obstructed by installed components.

First, all vias and footprints are known, since I've placed them on the backside of the board and KiCAD they of course reveal themselves on the front side. Wherever I see a via popping up under a component, I know it's probably going somewhere. So pull out the schematic with a highlighter and follow the via back on the back side of the board to where it ends up, and then figure out where it's going forward from there. Probably use two different colors of highlighter, one to indicate verified traces I've already 'traced' in KiCAD, the other to indicate a trace that is MIA on the top side due to component obscuring the view.

Same thing with tracks that run underneath an IC or component.

For totally invisible tracks that do not connect to a via, but rather between IC pins, I'll have to painstakingly go chip by chip with said highlighter looking for those connections and simply connect the dots so to speak, as a layout artist would have done back in the day.

At the end of the day the entire schematic should be covered in two colors of highlighter. Anything that isn't needs to be found and connected in KiCAD per the schematic.

I feel like at the end of the day, the top side of the CPU board will not be 100% exact as original, but it'll be fairly close. Traces only have so many pathways available to get to a place, so whatever I have to 'make up' from the schematic will probably tend to follow a similar path to what the original layout artist did.

Any flaws in my 'methodology' here? Is there a better way to do this?
 
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Day 3 of the Sphere project and I've made quite a bit of progress. All but handful of vias are in place, footprints are all done, and about 3/4 of the back side of the board is now traced.

To quell my ADD, I decided to take a stab at following the schematic around and making a couple of connections that were hidden underneath a 6842 at E51. I'm using red highlighter in Acrobat to mark connections, in straight lines, that were already made on the top side of the board, and blue to mark connections already made on the backside of the board. Not really original, basically the default colors for Side 1 and 2 in KiCAD. So far the schematic seems to line up nicely with 'facts on the ground'. I made couple of connections that went under 6842 (marked as squiggly red). Obviously I don't know the *exact* path of those traces that the layout artist took, but it looks like on the other side of the board, wherever he had a trace running between sides of an IC, they did a straight horizontal line and then 45 or so down to the pin. So I'm aping that in the hopes I get it fairly close. I'm hoping my efforts will spur Murphy's Law to surface an unbuilt CPU/2 board just to prove my guess wrong. :) Doesn't matter I suppose - long as a trace makes the connection and doesn't cross over other traces. In a way, it feels like being the long ago layout artist, trying to figure out how to bring the schematic to board form. Just a little! Plan remains to do the entire backside first though before working the topside.

Tracing seems to be pretty easy - the designer eschewed curvy traces in favor of straight lines. Pin 1 for ICs is marked on the underside by just a short length of wide 4x tape. The big ground planes are kind of weird shaped.
 

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The front is done! Well, mostly.. still have to add some symbols and letters and numbers, and there's a ton of tweaking to do, but the basic board is there. I did kinda get some help from Ben with some really detailed scans he took of his boards, so that let me bypass the schematic mysteries this time. But that won't be possible on other boards like the CRT board.
 

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Hi all - my GitHub repo has the CPU/2 board all documented and done - Ive built it but stalled on testing it due to power issues. I will post here some images tomorrow when I get to take them. My repro board is a millimetre (AFAIK) accurate of the original.....
 
In fact, I realised that since I have less than 10 posts here I can't post media i.e. the pix I have of my board that I have reconstructed etc. I will probably pop them in my GitHub repo and post the link here for you to see. In the meantime, here's my KiCAD trace of the CPU/2 board : https://github.com/Sphere-Corporation/CPU-2000 and here's my documented earlier (but with useful info of the CPU/2 board - with annotated investigation of the schematic etc) https://github.com/Sphere-Corporation/CPU-2
 
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Thanks very much for this!
I have successfully used your link and retrieved your document.
Please keep posting your progress.
smp
 
I missed this thread earlier-- somehow I didn't see the notification when @snuci tagged me-- sorry! I've been consumed with getting my Sphere book out the door. (I have more boxes of them if anyone is interested in this computer and company!) Anyway, I'm glad Andrew found his way here -- he and @falter are the only folks I've been aware of working on something like this.

To the extent anyone is testing a board out, I have accumulated (for better and worse) a fair bit of experience smashing my head against aka troubleshooting nonworking Sphere hardware. I've posted diagnostic programs I whipped up to my software page (under Utilities & Diagnostics) and happy to provide guidance/advice if I'm able.

I still don't have a way to program 1702as

I do, and can help with sets of the firmware EPROMs if needed.
 
Ben I will buy one of your books for sure!

I am hoping to get my first board set produced within the next few weeks.. if you like I can send you one gratis to see how it compares to the blank you have. Your knowledge in troubleshooting these things would be a massive help, when and if you get time.

I actually have vintage unused PCB stock of sufficient size so I plan to make at least one board, somehow, using that.
 
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