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TANO Dragon 64 - CoCo SDC not working?

LambdaMikel

Experienced Member
Joined
Jan 25, 2020
Messages
277
Folks, my CoCo SDC works fine in my CoCo II (US Rev B), and I just updated the firmware yesterday. However, I can't get it to work in my TANO Dragon.
I have set the jumpers like in the picture attached, and I am getting the DOSPLUS 5.0. However, from there, I am unable to do anything. Trying to mount a drive VDK or DSK image, I am always getting some weird error messages. And I can't find any documentation. I am assuming that there is something wrong with my TANO? Cartridges and 3.5" floppy disk also work well, but I didn't have luck with a 5.25 color computer mini drive (for that, I am using Ian Mavric's replicate disk controller). Anyhow, that's a different issues.

I tried mounting a VDK / DSK image using DRIVE 0, "DISK.VDK" (DRIVE 1, "DISK.DSK" etc.), as well as MOUNT 1, "DISK.VDK" (and also with and without .DSK / .VDK extension). I can also see the drive activity LED coming on. But then, I usually get some error. DRIVES doesn't work either. The SDC is working fine with the CoCo II. Not sure what I am doing wrong? I am not sure why none of this is documented in the CoCo SDC manual...
 

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OK, problem solved....

Dear CoCo SDC makers, can you please add a word or two the the manual mentioning DOSPLUS commands such as SDRIVE? It is extremely difficult to find this information online!
 
Last edited:
I was just wondering why...

Normally, putting pull-ups on the address bus and read/not write signal indicates a problem with the CPU releasing the bus. I see (from looking at the schematics) that the TSC (Tristate Control) pin is grounded, thus preventing the 6809 CPU from relinquishing control of the bus (from a hardware perspective).

Reading the text on the SYNC instruction doesn’t actually make it clear whether or not execution of this instruction causes the 6809 CPU to relinquish the bus. Looking at the hardware timing diagrams - IT DOES.

This indicates that the address and data busses plus the control lines (including read/ not write) are tristated, and therefore float, during the execution of the SYNC instruction.

This could cause any address location (memory or I/O devices) to be accessed during this period of time, with potentially disastrous results.

Adding pull-up resistors guarantees that memory address 0xFFFF is READ. This is part of the ROM code and would be benign in operation.

This is why the modification works.

The CPU contains an output signal (BA - Bus Acknowledge) that goes HIGH when the 6809 releases the bus. On the schematic, BA is not wired. If this signal had been used to disable memory and device access, all would have been well.

This is possibly a case where the software guys have used an instruction that has an impact on the hardware design that wasn’t catered for. Inter team communication (or rather, lack of).

LambdaMikel, can I suggest adding your location to your profile?

Dave
 
@daver2 yes interesting case. I should note though that I don't have that problem. After I found SDRIVE from the video, I am able to use the CoCo SDC without issues on my TANO.
 
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