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The old Z16C04 SBC project from https://z8000.neocities.org

Interesting but Siemens did do a couple of Z8000 based control boards, but nothing else externally. As with your detailed proposal and design , if it was copywrite or patented before it was submitted to them, them you could try to get your development cost back. But the legal fees' might exceed its cost. I have had been through hostile takeovers (for product suppression) so I can relate to that.
This was, AFAIKR, 1979. I knew some of the people on the AMC software team and at least one of their managers. It was a ship of fools. The whole operation was history by about 1981. AMD got out of the Z8000 business by then and became a second source of the 8086; strategically a better decision.

Al Kossow:

If you're interested in a few old AMC manuals, I have them in pristine condition, since I never bothered with any of them. Drop me a line and I'll get them off to you.
 
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Cool somebody noted a Olivetti L1M20, I have several Olivetti l1 family members still in active service outside of North America for work. As far as Z80ne.com in the past I have sent them the details on the L1M20 revisions G and H motherboards, but it never got posted at the web sight. Some newer revisions of the motherboard supported more than 512K of memory on board.
I'm not sure how one would support more than 512K, with ROM based memory management. The M20 used a ROM based memory management that meant that reaching the 1024K would require active memory management. I'm not saying it couldn't be done, just that it would have been difficult, without some form of active address select register to redirect additional segments. The ROM system consumed, all the native Z8000 segments ( with many holes ). Any additional memory would have needed some type of memory swapping method.
The ROM based system was used to double map segments of memory for splitting out data memory and instruction memory, as part of the protection for code. This way it was difficult for say a BASIC program to modify machine code by accident. There of course were ways around this at the machine code level. The idea was that BASIC could then only access data memory.
Dwight
 
Olivetti made a Z8000 based computer. They ran PCOS and CP/M - ported over in C - as an operating system. That means there is a native assembler and at least a C compiler available for it.
They also created a very big computer, sized like a PDP or mainframe. I ran into it when having a course somewhere in 1993. I was told I could take out parts if I wanted to because it was to be scrapped. That's how I ended up with three Z8001s, one Z8002 and four Z8010s.
I always had the idea of using them one day and so far it just stayed an idea. But if anyone feels the need to create a small SBC board, I will be interested. I'm even willing to donate some of the parts to the project.
 
On the standard 1LM20 the following microprocessors address lines output A16(SN0), A17(SN1) , A18(SN2), A19(SN3) are active (and run to the expansion bus). (Below Olivetti/Docutel L1M20 model revisions G and H models, ) the SN4 to SN6 are logically connected to trip the Segment Trap signal. On others models like the L1M40, L1M60 these signals are used.
As far as the memory mapping ROM is concerned in the L1M20 revision G and H mother boards theirs a couple more jumper inputs to it. Yes, the Coding on the Memory management Prom can also be different (as in some models). To save some time and space I skip the use of the Zilog 8010 MMU that is used in larger L1 family of computers.
..
Systems with 256K on the mother board
--------------------------------------------
(1 year of production) On the 256K Latin American(&Eastern Block/Japanizes clone) models, their is a jumper setting for two banks of 128K Dram chips on the motherboard. The memory expansion slots has a couple of the unused pins reserved for this. These slots support 3 cards with 2 banks of 128K each.
..
Systems with 512K on the mother board
---------------------------------------------
AS for the motherboards with 512K Dram on board, their are addition circuit traces that is not connected on the older models with 128K or 64K only on board.
I have already noted about extra signal lines used for the memory expansion slots above. Unconnected on L1M20 below model revisions G and H models.
..
The memory mapping PROM
Their is a couple of jumper settings that change a couple on the inputs to the memory mapping PROM. I would have to dig out my old documents, and probably rescan them). It basically changes them form their default inputs and add two new ones. Other then +5V volts, GND, Or the old defaults as showed in the North American Schematic set.
To save some time and space, I would not note about enhanced memory overlays and remapping.
..
Anyways thanks for your reply.
 
They also created a very big computer, sized like a PDP or mainframe. I ran into it when having a course somewhere in 1993. I was told I could take out parts if I wanted to because it was to be scrapped. That's how I ended up with three Z8001s, one Z8002 and four Z8010s.
I always had the idea of using them one day and so far it just stayed an idea. But if anyone feels the need to create a small SBC board, I will be interested. I'm even willing to donate some of the parts to the project.
Yes I am very interested in them, Even if their are not from a L1M family of systems. Others like BCS 2X99 , S6000, and other models, I could always use. If you have them handy their is a part number on them, that would identify what system their from. I might be ably to reuse them directly. I have attached 2 photos from a L1M33 PCB.
==== You can always direct message me for the liquidation of them
 

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This was, AFAIKR, 1979. I knew some of the people on the AMC software team and at least one of their managers. It was a ship of fools. The whole operation was history by about 1981. AMD got out of the Z8000 business by then and became a second source of the 8086; strategically a better decision.

Al Kossow:

If you're interested in a few old AMC manuals, I have them in pristine condition, since I never bothered with any of them. Drop me a line and I'll get them off to you.
I thank you for your reply from Mar 11, 2022, but I was not to sure how much help to me they would actually be, other their their IC's and other contents. So for this reason and my work level at the time, I did not reply. Thanks' for the offer.
 
But it's a closely-related thing :->. Just pointing out a proven SBC design in case anyone passes by and thinks "gee, maybe I want to try out a Z8000" as a new hobby project. Not everyone will want to jump into the deep end of the Z8000-pool with segmented memory on their first outing (assuming that they can even find the necessary parts). And then there's the general issue of software-lack given market failure. One challenge at a time ...
Anyways about this older reply, If you really want to do a Z8000 based project and have a old IBM PC compatible with a ISA related expansion bus. Then maybe you should look into the old byte magazine built the trump card article. As this add on card does not use any MMU or other hard to get semiconductors, it is simple to get the parts for, but the missing software is a another issue. (other then using it as a RAMDISK/Print Buffer).
..
The for the old Olivetti L1M20 design, other them its Memory mapper PROM and the none IBM PC standard floppy disk drive pinout should be easy to obtain the parts for.
AS for a more complex system theirs the Elektro-Apparate-Werke. P8000 at http://www.pofo.de/P8000/ You would have to get him to dump the firmware and software.
..
As for Z8000 based systems like the Zilog System 8000 family, I really don not recommend it, basically because of the items you would have to try to acquired to build one system.
Aka ! the software, Intact OS recovery tapes, A Diskbus compatible hard disk (If no SMD interface), and other related parts. The archives I have cone across have been incomplete, Their archive OS files have not been the right size (files missing) for the system they stated.
..
The AMD multibus board could be another possibility. I wasn't to sure how much you where really interested, in doing so, So I did not reply until now.
 
No matter; I sent them off to Al K. for inclusion in bitsavers.
Right On - sent for bitsavers.org. Archive. Hopefully they add it to their archives soon. (to many just throw them out, or use it for fire starter).
 
The Z8002 isn't quite the same thing, is it? Basically a Z8000 without the segmentation. Great for embedded use, however.
Most of the un-segmentation Z8000 I have dealt with still used some sort of bank switching for memory expansion. Or They where used as some kind of coprocessor or I/O controller. So I get it.
 
On the standard 1LM20 the following microprocessors address lines output A16(SN0), A17(SN1) , A18(SN2), A19(SN3) are active (and run to the expansion bus). (Below Olivetti/Docutel L1M20 model revisions G and H models, ) the SN4 to SN6 are logically connected to trip the Segment Trap signal. On others models like the L1M40, L1M60 these signals are used.
As far as the memory mapping ROM is concerned in the L1M20 revision G and H mother boards theirs a couple more jumper inputs to it. Yes, the Coding on the Memory management Prom can also be different (as in some models). To save some time and space I skip the use of the Zilog 8010 MMU that is used in larger L1 family of computers.
..
Systems with 256K on the mother board
--------------------------------------------
(1 year of production) On the 256K Latin American(&Eastern Block/Japanizes clone) models, their is a jumper setting for two banks of 128K Dram chips on the motherboard. The memory expansion slots has a couple of the unused pins reserved for this. These slots support 3 cards with 2 banks of 128K each.
..
Systems with 512K on the mother board
---------------------------------------------
AS for the motherboards with 512K Dram on board, their are addition circuit traces that is not connected on the older models with 128K or 64K only on board.
I have already noted about extra signal lines used for the memory expansion slots above. Unconnected on L1M20 below model revisions G and H models.
..
The memory mapping PROM
Their is a couple of jumper settings that change a couple on the inputs to the memory mapping PROM. I would have to dig out my old documents, and probably rescan them). It basically changes them form their default inputs and add two new ones. Other then +5V volts, GND, Or the old defaults as showed in the North American Schematic set.
To save some time and space, I would not note about enhanced memory overlays and remapping.
..
Anyways thanks for your reply.

I made a "modern" M20 clone and I am running PCOS & CP/M 8K on it (with the original 2.0f bios). I agree that one could use SN4-SN6 to support more than 512K, but the 2.0f bios certainly wouldn't use the extra memory, because
it actually checks for SEGT trap on segment 7 during POST. Do you know of bios & PCOS versions supporting more than 512k?
 
Hay, thanks for your reply. Yes I know about some of the L1M20 bios (firmware) limitations. At one time there was a driver for PCOS and other operating systems for the L1M20, that would let you use more than 512K. Unfortunately nobody keep any clean archive copies of it. The original RAMDISK driver, nobody seems to keep, the same for any 3Rd parity EMS memory boards for the L1M20. As far as bios upgrade any version of a machine that has 41128 or 4256 drams on the motherboard that support memory to at least 640K should work. (AkA ! base memory of 256K in two 128K banks or 512K on board in two 256K banks.)
Bios Firmware greater than 2.0F. Probably any BIOS from after the (APB8086) was released should probably give you up to 640K plus under MS-DOS. (I have noted elsewhere about a MS-DOS, CP/M memory patch).
..
As far as older PCOS versions are concerned, If it is from a Olivetti M24 PC compatible, yes it should see more than 512K, But the hardware in a olivetti M24 PC is different from a L1M2x so it would have to be patched. Onboard firmware code copied and patch for hardware differences. PCOS versions above 4.8 for the L1M20 support it. With CP/M 8K we just patched another driver form a different CP/M 8K that supported more than 512K.
..
In your message you did not state what PCOS version or CP/M 8K you are using or if you have a intel x86 coprocessor card (APB8086). Depending on the OS this will affect the addressing region that would have to be patch, (due to the os version different locations).
..
The method most use in Latin America is to re cross-compiler, or use microprocessor converters utilities to convert the patch for old versions of MS-dos and CP/M86 to see more than 256K or 512K of memory.
Their used to be microprocessor converters utilities that could port a PC-dos X86 executables and files to/and from a CP/M 86 version. Then convert a CP/M86 to a CP/M 8K or PCOS version.
..
Most of the larger L1M series we have still in service use a different os. A UNIX/XENIX clone, Or their other os that will still run PCOS applications. MP/MN 8K with the GSX extensions installed. Other then a time crunch their could be some possible legal issues for me to disassemble a complete OS back to source code (, for none client related work).
..
As for the BIOS actually check for SEGT trap issues on segment 7 during POST, yes but that can be redirected. Some Bus adapter boards did that for the L1M20 in hardware. On the L1M20, its Memory Management Unit a 82S181 PROM has a enable/disable input pin. This pin number 18 is a input signal used by the /MEMDIS signal from the systems expansion bus to disable or enable the MM PROM. The rest of the hardware on adapter board other then the I/O logic the just watches for SEGT trap issues on segment 7 with the correct microprocessor status cycles and then switches the overlay on or off.
..
The Olivetti L1M20 is a easier system to add memory to it over the 512k region than the a IBM PC to support more conventional memory than 640K of base memory. IBM did not put the full Intel microprocessor status cycles signals lines on to the ISA Bus. Companies like MICROWay used a custom programed MCU as a MMU to support DOS conventional memory to 1016M. It also emulated the missing Intel signal pins, read the microprocessors instructions (for the correct code segment page and etc). Some other manufactures memory board had extra leads that you had to reattached to the PC's intel microprocessor corresponding pins. Normally it is the pins for A16/S3, A17/S4, A18/S5, A19/S6, so the board can see the full microprocessor code and status cycles). At least Olivetti had the smarts to include them on their expansion bus (, unlike IBM)
..
I have noted this to you for the fact that you could convert a bus adapter to do so it needed. Note that the Intel x86 coprocessor (APB8086) board/card uses a different address then on the Olivetti M24 PC. The ISA adapter for the L1M20 normally found on line is quite buggy/limited, so if you do not have any bus conflicts, I would wire a direct 16-bit ISA bus-to-bus adapter with address translations for the L1M20 and M24 PC. To note the address translations in this posting would take up some space and time to retype/scan. The old MS-dos files for the external Ebios.sys, EGA emulation, ANSI Emulation extension for the Intel X86 card can no longer be relocated online. The Olivetti M21 & M24 Theory Of Operation is available for downloading. Old L1M20 Address range for the Intel x86 coprocessor (APB8086) was in the 7FXA to 7FXF (hex) range, other ISA card I/O address where repaped somewhere in the 7xxx (Hex) range. The old Ebios.sys remaps other hardware I/O to that range. The Intel 8087 APU adapter board also sat somewhere in that area.
..
Since you built your own Olivetti L1M20 clone, I hope this helps point you to a possible solution.
 
I'm not sure how one would support more than 512K, with ROM based memory management. The M20 used a ROM based memory management that meant that reaching the 1024K would require active memory management. I'm not saying it couldn't be done, just that it would have been difficult, without some form of active address select register to redirect additional segments. The ROM system consumed, all the native Z8000 segments ( with many holes ). Any additional memory would have needed some type of memory swapping method.
The ROM based system was used to double map segments of memory for splitting out data memory and instruction memory, as part of the protection for code. This way it was difficult for say a BASIC program to modify machine code by accident. There of course were ways around this at the machine code level. The idea was that BASIC could then only access data memory.
Dwight
Thank you for your reply.
Memory Management on the L1M20 is possible quite simply, Other members of the L1M family have larger memory sizes, even on machines that did not use the zilog Z8010 MMu chip. In a another message I have already noted about other l1M family members. On L1M20 below models G and H only SN0 to SN3 are used, so in theory there's 1024K available. That is 512K in memory on board in the motherboard with memory expansion cards and another 512K is available on the expansion bus card slots. Since several bus adapters let you use more memory than 1024K just by using mostly xxlsxxx logic chips on them., (with a BIOS firmware fix, memory extension drivers). In this message I will not include any memory address overlay addressing or specificant memory type overlays.
..
The L1M20 Memory Management Unit PROM can be directly disabled by its Pin 18. This input is used by /MEMDIS signal from the expansion bus to disable or enable the MM PROM.
This semiconductor is normally a 82S181 PROM, that is only a1024K by 8 bit device. There is only 4 disable input pins for it. - 2 are active low. Yes this chip does not use ST0 signal. It does not full decode the status inputs given to it. (Their are used to temporary disable or rein able it, update its output registers. That is about it for the ST1, ST2, ST3 signal lines used)
Pin 21 is pulled to GND (ground) to keep /CE0 at a logic 0 state to help this chip stay active.
Pin 20 is ST1 input that is used to pull /ce1 input up or down -
Pin 19 is ST3 input that is used to pull CE2 input up - Logic "1" to activate it
Pin 18 a input is used by /MEMDIS signal from the expansion bus to disable or enable the MM PROM.
(It is noted in most manuals) Pin 3 is a ST2 input.
(It is noted in most manuals) Pin 1 is the B&W/-Color memory select input.
* SRAM output on 16 from the Memory Management PROM is used to select the RAM on the VideoTex and/or the 3rd parity video capture board, some cache buffers.
..
Motherboard Jumper Z settings with use of the Memory Management PROM .
Z1 = use SN3 input on pin 2, but if jumper Z2 is use. Then it uses 32K//128K signal as input on pin 2 of Memory Management PROM. Jumpers Z3 and Z0 have been omitted.
..
Active L1M20 address select register to redirect additional segments. Unlike the IBM PC"s ISA bus the Olivetti has all the microprocessors Status signals available on its expansion bus. (excluding the Multiprocessor lines), so access to them is simple. Easy to decode all the microprocessors status and cycles without wiring extra leads (back to the microprocessor as in the IBM PC design for more than 640K of base memory). The MMU external override signal is already there (/MEMDIS) and all the other required are already on the extension bus signals. As already noted, Yes, the MMU ROM based system was used to double map segments of memory for splitting out data memory and instruction memory, as part of the protection for code, But control signals are available on the expansion bus connectors. An Address select register to redirect additional segments is not to complex to generate in login. On other Z8000 based systems an intelligent MCU programed as A MMU reads the Z8001 Program Status Registers information and the microprocessors Status and SN signals to inturted the operation.
..
As for accessing the first 1024K of memory it can simply be done without a active memory management. Really Just A19/SN3 and the Z8000 Status Signals feed into a decoded PROM to separate the different memory type functions, or a bunch if logic chips could be used.
..
As already noted Below Olivetti/Docutel L1M20 model revisions G and H models, ) the SN4 to SN6 are logically connected to trip the Segment Trap signal. On others models like the L1M40, L1M60 these signals are used,.Memory Mapping PROMS are different, L1M21 (Not the M21 IBM PC compatible) and above have additional hardware in them that the L1M20 and below models don't have.
 
If somebody wishes to do a full Olivetti L1M20 memory map for the memory region above 512K with the proper memory code type listed (Microprocessor Memory type Function) in use, Please do so.
I have not done so to save myself some time and our forum provider some space. If you wish to provide this data please include what function code space microprocessor is using. (In other words what's the Z8000's status signal output to that block of memory. Data or Stack Space, Normal/System Mode, Instruction or Instruction Data space, Program Reference space. On all Z8000 based system it is possible to have separity (private) memory spaces for each of the processors operation cycles, so some additional decoding is used.
..
..
 
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Hay, thanks for your reply. Yes I know about some of the L1M20 bios (firmware) limitations. At one time there was a driver for PCOS and other operating systems for the L1M20, that would let you use more than 512K. Unfortunately nobody keep any clean archive copies of it. The original RAMDISK driver, nobody seems to keep, the same for any 3Rd parity EMS memory boards for the L1M20. As far as bios upgrade any version of a machine that has 41128 or 4256 drams on the motherboard that support memory to at least 640K should work. (AkA ! base memory of 256K in two 128K banks or 512K on board in two 256K banks.)
Bios Firmware greater than 2.0F. Probably any BIOS from after the (APB8086) was released should probably give you up to 640K plus under MS-DOS. (I have noted elsewhere about a MS-DOS, CP/M memory patch).
..
As far as older PCOS versions are concerned, If it is from a Olivetti M24 PC compatible, yes it should see more than 512K, But the hardware in a olivetti M24 PC is different from a L1M2x so it would have to be patched. Onboard firmware code copied and patch for hardware differences. PCOS versions above 4.8 for the L1M20 support it. With CP/M 8K we just patched another driver form a different CP/M 8K that supported more than 512K.
..
In your message you did not state what PCOS version or CP/M 8K you are using or if you have a intel x86 coprocessor card (APB8086). Depending on the OS this will affect the addressing region that would have to be patch, (due to the os version different locations).
..
The method most use in Latin America is to re cross-compiler, or use microprocessor converters utilities to convert the patch for old versions of MS-dos and CP/M86 to see more than 256K or 512K of memory.
Their used to be microprocessor converters utilities that could port a PC-dos X86 executables and files to/and from a CP/M 86 version. Then convert a CP/M86 to a CP/M 8K or PCOS version.
..
Most of the larger L1M series we have still in service use a different os. A UNIX/XENIX clone, Or their other os that will still run PCOS applications. MP/MN 8K with the GSX extensions installed. Other then a time crunch their could be some possible legal issues for me to disassemble a complete OS back to source code (, for none client related work).
..
As for the BIOS actually check for SEGT trap issues on segment 7 during POST, yes but that can be redirected. Some Bus adapter boards did that for the L1M20 in hardware. On the L1M20, its Memory Management Unit a 82S181 PROM has a enable/disable input pin. This pin number 18 is a input signal used by the /MEMDIS signal from the systems expansion bus to disable or enable the MM PROM. The rest of the hardware on adapter board other then the I/O logic the just watches for SEGT trap issues on segment 7 with the correct microprocessor status cycles and then switches the overlay on or off.
..
The Olivetti L1M20 is a easier system to add memory to it over the 512k region than the a IBM PC to support more conventional memory than 640K of base memory. IBM did not put the full Intel microprocessor status cycles signals lines on to the ISA Bus. Companies like MICROWay used a custom programed MCU as a MMU to support DOS conventional memory to 1016M. It also emulated the missing Intel signal pins, read the microprocessors instructions (for the correct code segment page and etc). Some other manufactures memory board had extra leads that you had to reattached to the PC's intel microprocessor corresponding pins. Normally it is the pins for A16/S3, A17/S4, A18/S5, A19/S6, so the board can see the full microprocessor code and status cycles). At least Olivetti had the smarts to include them on their expansion bus (, unlike IBM)
..
I have noted this to you for the fact that you could convert a bus adapter to do so it needed. Note that the Intel x86 coprocessor (APB8086) board/card uses a different address then on the Olivetti M24 PC. The ISA adapter for the L1M20 normally found on line is quite buggy/limited, so if you do not have any bus conflicts, I would wire a direct 16-bit ISA bus-to-bus adapter with address translations for the L1M20 and M24 PC. To note the address translations in this posting would take up some space and time to retype/scan. The old MS-dos files for the external Ebios.sys, EGA emulation, ANSI Emulation extension for the Intel X86 card can no longer be relocated online. The Olivetti M21 & M24 Theory Of Operation is available for downloading. Old L1M20 Address range for the Intel x86 coprocessor (APB8086) was in the 7FXA to 7FXF (hex) range, other ISA card I/O address where repaped somewhere in the 7xxx (Hex) range. The old Ebios.sys remaps other hardware I/O to that range. The Intel 8087 APU adapter board also sat somewhere in that area.
..
Since you built your own Olivetti L1M20 clone, I hope this helps point you to a possible solution.
Hi,
I am running PCOS 4.0b & 4.1. Never heard about a PCOS 4.8...
I cloned a complete M20BC, without the APB 8086 card. I might create an APB8000 card for the M24, it should be pretty simple at this point.
On my clone I actually have 1MB of RAM, but I am only using 512K (and 8K for the ROM) and the video ram is on a separate DPRAM which drives
a VGA signal.
Since I recreated the original memory scheme on a PLD, I can easily map additional segments and get rid of the segment trap.
You may be right regarding the APB8000 board in the M24. I read the manual again and it says that PCOS supports up to 512K or ram and 128K of video memory, while in the
M20 the video memory is included in the 512K addressed. I'll take a look at the differences in the reported memory segments between PCOS on the M20 and PCOS on the APB8000.

Thanks!
 
Hi,
I am running PCOS 4.0b & 4.1. Never heard about a PCOS 4.8...
I cloned a complete M20BC, without the APB 8086 card. I might create an APB8000 card for the M24, it should be pretty simple at this point.
On my clone I actually have 1MB of RAM, but I am only using 512K (and 8K for the ROM) and the video ram is on a separate DPRAM which drives
a VGA signal.
Since I recreated the original memory scheme on a PLD, I can easily map additional segments and get rid of the segment trap.
You may be right regarding the APB8000 board in the M24. I read the manual again and it says that PCOS supports up to 512K or ram and 128K of video memory, while in the
M20 the video memory is included in the 512K addressed. I'll take a look at the differences in the reported memory segments between PCOS on the M20 and PCOS on the APB8000.

Thanks!
Thank you for your reply.
Memory Management on the L1M20 is possible quite simply, Other members of the L1M family have larger memory sizes, even on machines that did not use the zilog Z8010 MMu chip. In a another message I have already noted about other l1M family members. On L1M20 below models G and H only SN0 to SN3 are used, so in theory there's 1024K available. That is 512K in memory on board in the motherboard with memory expansion cards and another 512K is available on the expansion bus card slots. Since several bus adapters let you use more memory than 1024K just by using mostly xxlsxxx logic chips on them., (with a BIOS firmware fix, memory extension drivers). In this message I will not include any memory address overlay addressing or specificant memory type overlays.
..
The L1M20 Memory Management Unit PROM can be directly disabled by its Pin 18. This input is used by /MEMDIS signal from the expansion bus to disable or enable the MM PROM.
This semiconductor is normally a 82S181 PROM, that is only a1024K by 8 bit device. There is only 4 disable input pins for it. - 2 are active low. Yes this chip does not use ST0 signal. It does not full decode the status inputs given to it. (Their are used to temporary disable or rein able it, update its output registers. That is about it for the ST1, ST2, ST3 signal lines used)
Pin 21 is pulled to GND (ground) to keep /CE0 at a logic 0 state to help this chip stay active.
Pin 20 is ST1 input that is used to pull /ce1 input up or down -
Pin 19 is ST3 input that is used to pull CE2 input up - Logic "1" to activate it
Pin 18 a input is used by /MEMDIS signal from the expansion bus to disable or enable the MM PROM.
(It is noted in most manuals) Pin 3 is a ST2 input.
(It is noted in most manuals) Pin 1 is the B&W/-Color memory select input.
* SRAM output on 16 from the Memory Management PROM is used to select the RAM on the VideoTex and/or the 3rd parity video capture board, some cache buffers.
..
Motherboard Jumper Z settings with use of the Memory Management PROM .
Z1 = use SN3 input on pin 2, but if jumper Z2 is use. Then it uses 32K//128K signal as input on pin 2 of Memory Management PROM. Jumpers Z3 and Z0 have been omitted.
..
Active L1M20 address select register to redirect additional segments. Unlike the IBM PC"s ISA bus the Olivetti has all the microprocessors Status signals available on its expansion bus. (excluding the Multiprocessor lines), so access to them is simple. Easy to decode all the microprocessors status and cycles without wiring extra leads (back to the microprocessor as in the IBM PC design for more than 640K of base memory). The MMU external override signal is already there (/MEMDIS) and all the other required are already on the extension bus signals. As already noted, Yes, the MMU ROM based system was used to double map segments of memory for splitting out data memory and instruction memory, as part of the protection for code, But control signals are available on the expansion bus connectors. An Address select register to redirect additional segments is not to complex to generate in login. On other Z8000 based systems an intelligent MCU programed as A MMU reads the Z8001 Program Status Registers information and the microprocessors Status and SN signals to inturted the operation.
..
As for accessing the first 1024K of memory it can simply be done without a active memory management. Really Just A19/SN3 and the Z8000 Status Signals feed into a decoded PROM to separate the different memory type functions, or a bunch if logic chips could be used.
..
As already noted Below Olivetti/Docutel L1M20 model revisions G and H models, ) the SN4 to SN6 are logically connected to trip the Segment Trap signal. On others models like the L1M40, L1M60 these signals are used,.Memory Mapping PROMS are different, L1M21 (Not the M21 IBM PC compatible) and above have additional hardware in them that the L1M20 and below models don't have.

If somebody wishes to do a full Olivetti L1M20 memory map for the memory region above 512K with the proper memory code type listed (Microprocessor Memory type Function) in use, Please do so.
I have not done so to save myself some time and our forum provider some space. If you wish to provide this data please include what function code space microprocessor is using. (In other words what's the Z8000's status signal output to that block of memory. Data or Stack Space, Normal/System Mode, Instruction or Instruction Data space, Program Reference space. On all Z8000 based system it is possible to have separity (private) memory spaces for each of the processors operation cycles, so some additional decoding is used.
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Olivetti L1M20 memory expansion above 512k and the L1m20 memory map. (ops last posting still hade some type "o"s)
As I already posted most on the L1M series, I still have access to are more advanced then the L1M20.
PCOS above 4.1 did exist but was used in mostly University/Post secondary Institutes. Most versions after 4.1 are based of the L1M30 or greater line MOS operation system. (in short) They where re patched to run on a standard L1M20 system.
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CP/M 8000 on the Olivetti L1M20 memory allocation above (512K) 524K solutions.
80000 Hex 524288 to 8FFFF Hex 589823 redecode a into two separate 64K banks for data and memory instructions.
90000 Hex 589824 to 9FFFF Hex 655359 redecode a separate bank for a instruction space at this location.
A0000 Hex 655360 to AFFFF Hex 720895 was dual mapped.
B0000 Hex 720896 to BFFFF Hex 786431 Old Memory mapped Floating point hardware.
== Memory management prom fixes - could be needed depending on version, already installed in the system.
== Operating systems patch, may also be needed.
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Other memory locations
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C0000 Hex 786432 to CFFFF Hex 851967
D0000 Hex 851968 to DFFFF Hex 917503 ( Can be used as a RAM Disk)
E0000 Hex 917504 to EFFFF Hex 983039
F0000 Hex 983040 to FFFFF Hex 1048575 On the L1M34 the Government Color Alphanumeric Video : GO224 uses a 8K Ram memory block.
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I have included some old MS-DOS memory utilities, but you will need the cross-converter and dissemblers/reassemble software it order to use then. Old PC-DOS to CP/M program executable converter, X86 to X80 executable converter, Likely a XX to Z8000 translator/converter program.
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Sorry but the Author did not provide the ASM code to fix bugs in it. the MOREDOS.*** And MOREMEM.*** do not have Intel code segment blocks in use, so some memory expansion cards above 512K will have problems with them. AS far as RAMDISK program called EDISK.*** it has its ASM code and uses Intel code segments CS, ES, DS but really any SS segments.
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Other files attached, Rel11Cpm(txtin2K2) is still downloadable with the included txt file.
============= The L1M34 Memory card jumper settings for their 1.0 to 2M byte boards.
 

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  • L1M33Memria_t2Mbrds.pdf
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  • EEM704.ZIP
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  • Emm704.txt
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  • 704RAM (1).ZIP
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At one time I originally posted about the old Z16C04 SBC project from https://z8000.neocities.org
But as far as the old Z16C0X SBC project, it seems to have run into a dead end. (Nobody reading these messages seams to have a complete archive copy). Thank you for your replyies.
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I might try for the missing Zilog System 8000 data later on.
 
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