Yes, it is cool, and does speed up string arithmetic and searching (great if you're interfacing with IBM systems). Just not used much these days.
Looking at the 11/44 docs for it, sounds like the board set is yet another full computer in there, 88 bit word, 1k in size. Anyone have a picture of the board? Does it really have 22 2901 bit slice processors on there?
The 11/23+ one is a lot simpler, 6 micro roms which I think let the main processor chew on very long micro-instructions to make it happen. Kind of like the KEF11. But 3 times the amount of data store to implement, so a hardware implementation in the 11/44 must be big.
Too bad DEC didn't go further with it, the KDJ11 Cpu does have pads on the bottom of the carrier for what I think was going to be CIS microms using the 11/73 sequencer. I wonder if the CIS option for the 11/70 just used the 11/44 boards in the same way the FPF11 works on the 23 and 24 systems (ie: watch the bus to decode a CIS instruction, then when you see one stall the CPU and take over the whole thing to do it, then return control to the CPU). That would explain the DMA snooping logic on the CIS for 11/44, since it's jamming the CPU it needs to watch out for DMA timeouts and suspend instructions as needed.
C
Looking at the 11/44 docs for it, sounds like the board set is yet another full computer in there, 88 bit word, 1k in size. Anyone have a picture of the board? Does it really have 22 2901 bit slice processors on there?
The 11/23+ one is a lot simpler, 6 micro roms which I think let the main processor chew on very long micro-instructions to make it happen. Kind of like the KEF11. But 3 times the amount of data store to implement, so a hardware implementation in the 11/44 must be big.
Too bad DEC didn't go further with it, the KDJ11 Cpu does have pads on the bottom of the carrier for what I think was going to be CIS microms using the 11/73 sequencer. I wonder if the CIS option for the 11/70 just used the 11/44 boards in the same way the FPF11 works on the 23 and 24 systems (ie: watch the bus to decode a CIS instruction, then when you see one stall the CPU and take over the whole thing to do it, then return control to the CPU). That would explain the DMA snooping logic on the CIS for 11/44, since it's jamming the CPU it needs to watch out for DMA timeouts and suspend instructions as needed.
C