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What is this microPDP-11?

Yes, it is cool, and does speed up string arithmetic and searching (great if you're interfacing with IBM systems). Just not used much these days.

Looking at the 11/44 docs for it, sounds like the board set is yet another full computer in there, 88 bit word, 1k in size. Anyone have a picture of the board? Does it really have 22 2901 bit slice processors on there?

The 11/23+ one is a lot simpler, 6 micro roms which I think let the main processor chew on very long micro-instructions to make it happen. Kind of like the KEF11. But 3 times the amount of data store to implement, so a hardware implementation in the 11/44 must be big.

Too bad DEC didn't go further with it, the KDJ11 Cpu does have pads on the bottom of the carrier for what I think was going to be CIS microms using the 11/73 sequencer. I wonder if the CIS option for the 11/70 just used the 11/44 boards in the same way the FPF11 works on the 23 and 24 systems (ie: watch the bus to decode a CIS instruction, then when you see one stall the CPU and take over the whole thing to do it, then return control to the CPU). That would explain the DMA snooping logic on the CIS for 11/44, since it's jamming the CPU it needs to watch out for DMA timeouts and suspend instructions as needed.

C
 
Nope, there was supposed to be a CIS option for the 70. As for plugging it in, if the boards for the 11/44 CIS are any guide it could have been a modified DD11 backplane plus connections into the processor. All it needs to do is watch the instruction stream, stall the processor and watch the unibus for interrupts.
 
I worked on the CIS option for the 11/70; it was the 11/74 CISP project. I have discussed it before here, I believe.
The 11/74 CIS was a three hex board set that went into an updated 11/70 backplane in slots 1-3, pushed other slots down, and eliminated one set of RH11 controller slots.
The CPU card set was basically that of the 11/70 with a couple of cards replaced with slight modifications.

When a CIS opcode was executed the CISP took control of the machine and ran its own microprogrammed engine to execute the instruction.
The CISP was designed for maximum performance execution, running the 11/70 memory at maximum bandwidth capability whenever it could.
It was 4K words of hightly optimized microcode controlling three separate datapaths in parallel, a decimal/string processor 16b path, a 32b integer datapath, and the 16b 11/70 cpu datapath.

The 11/44 CISP was a two board implementation (a datapath board and a control store board) that was just a basic get-it-done implementation. Performance was not the overall goal.
I have the CISP processor set in my 11/44 that I got via eBay a number of years ago.

I wish I had kept an 11/74 CISP board set, but they were too few in number, and it was never formally released as a product. I did manage to keep an 11/74 CISP plexiglass panel, however.

I have never heard of an 11/60 CIS implementation. I suppose someone could have used the WCS option to do it, but with only 1K words of space it would have been a really poor performer.

1174.jpg
 
Thank you for the information, very good to get that out in the world. I've always been interested in the microprogramming world, in one of my boxes I still have a WCS-11 from the 11/03 world. Not much one can do with it, but interesting.

So like the 44 it sounds like it was a true co-processor (as opposed to the CIS for the 23+ which was just endless microcode running through the F11 microsequencer). Do you have any pictures of the 11/44 unit, I'm curious if they just jammed in a bunch of 2901's like the FPP units or if it was something else.

I'm assuming the 70 was a better design than 2901's. I'll look up your posts.

Thanks!
C
 
Thank you for the information, very good to get that out in the world. I've always been interested in the microprogramming world, in one of my boxes I still have a WCS-11 from the 11/03 world. Not much one can do with it, but interesting.

So like the 44 it sounds like it was a true co-processor (as opposed to the CIS for the 23+ which was just endless microcode running through the F11 microsequencer). Do you have any pictures of the 11/44 unit, I'm curious if they just jammed in a bunch of 2901's like the FPP units or if it was something else.

I'm assuming the 70 was a better design than 2901's. I'll look up your posts.

Thanks!
C

Yes, both the 11/44 and 11/74 CIS units were separate co-processors. The CIS74 integer/descriptor processor was 2901 based, but the character/decimal datapath was custom logic, using classic 74181 ALUs and assorted translators programmed into PROMS. The CIS44 had a 16b 4-slice 2901 datapath. So some pictures ...

11/44 CIS datapath M7092 ...
1144_KE44-A_DATAPATH_M7092.jpg

11/44 CIS control M7091 ...
1144_KE44-A_CONTROL_M7091.jpg
 
Interesting, in the manual it said they used 1k of 80 bit micro-words, was wondering if they packed it full of 2901's.

I should dig out and post a picture of my FPF11, it's a total work of art how they got that hex sized thing into a little quad sized Q bus board.
 
Interesting, in the manual it said they used 1k of 80 bit micro-words, was wondering if they packed it full of 2901's.

I should dig out and post a picture of my FPF11, it's a total work of art how they got that hex sized thing into a little quad sized Q bus board.

Hmmm the FP11-F schematic indicates the uWord is 48b wide, implemented as 12(1Kx4) PROMs. Mostly under columns E72 and E80.
 
The 80 bit number was from the 11/44 CIS manual.

Sorry, when you mentioned the FPF11 I thought you were referring to the FPU and not the CIS...

The copy I have (EK-KE44A-TM-001_KE44-A_CISP_Technical_Manual.pdf) indicates the uWord is 1K x 88b, which corresponds to the 11 1Kx8 (82S181 equivalent) devices in the top row of the image of the card.

IIRC the uWord on the 11/74 CIS processor was 4K x 96 bits, and the uWord on the 11/74 CPU was extended to 1K x 68 bits from the original 11/70 CPU 256 x 64 bits (4 more bits for CISP communication).
 
Fun to hear all these little bits of information. I remember reading that the 11/70's microcode space was pretty tight, with all that extra memory was any work done in expanding the instruction set or making some of the instructions more efficient?

Last CIS type question for the group: I remember reading that the 11/03 also had some sort of a CIS option (CUS) that helped to speed up small Dibol 300 systems. Might have been like FIS (which was still kinda useful if small) does anyone remember that concept, and could one load the microcode into an 11/03 WCS?
 
Fun to hear all these little bits of information. I remember reading that the 11/70's microcode space was pretty tight, with all that extra memory was any work done in expanding the instruction set or making some of the instructions more efficient?

The 11/70 to 11/74 microcode update was purely for support of the CISP option, no changes were made to the standard PDP-11 instruction flows
EXCEPT that the ASRB instruction was re-implemented as an atomic memory lock operation, so when it would read memory, operate on it, and write back, in an interlocked fashion.
No intervening memory operations allowed between the read and write. Strictly speaking this was a mod from the 11/70MP program, and not CIS related per se.

When the CISP ran, it took over the 11/70 micro PC and a 10b field from the CISP 96b uword was used as the base CPU uPC index. So the extended uword space was basic a set
of predefined microword options the CISP could order the base 11/70 CPU could execute. This is how the CISP did memory reads/writes for example, using the 11/70 CPU.
 
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