When did Zilog remove the RFSH signal from the z80?

[cj7hawk]

I guess I'm never too old to learn something I never would have thought true had it not been for the source of the information.

How did the Z80's automatic DRAM refresh feature improve the reliability and performance of systems compared to other processors of its t...

Answer: Designing the Osborne-1 computer I was able to make use of the “REF” signal from the Z80 to time the video screen refresh. I used a cheap and multiply-sourced LSI counter chip of Motorola design to provide the stream of screen access addresses and avoided the need for an expensive (and th...

www.quora.com

When did Zilog remove the RFSH pin signal, and what did they replace it with? I don't think I've seen a datasheet that had something else there?

A nice change for this pin would have been to make the R register 8 bits instead of 7, but the whole backwards compatibility result would have been problematic.

The 2016 user manual shows it still there, so I'm wondering when it disappeared? ( https://www.zilog.com/docs/z80/um0080.pdf )

David

 

[cj7hawk]

This is not the only time Lee Felsenstein has mentioned this -

Why was the Z80 so popular with manufacturers compared to the i8080, and what specific features made it easier to work with?

Answer: The 8080 required a 12-volt 2-phase clock with stringent rise and fall times — the Z80 required only a 5-volt single-phase clock. The 8080 ran at 2 MHz and the Z80 ran at 4 MHz. The CP/M operating system would run unmodified on the Z80 — there were many Z80 upgrade boards offered specifi...

www.quora.com

Which really does lead me to wonder how often I may have tripped over this issue myself?

 

[Bruce Tomlin]

Oh — Zilog eventually removed the REF signal from their Z80 — anyone attempting to replicate the circuit will have to use legacy chips.

They didn't remove it from the 40-pin Z80 chip (they one they recently stopped manufacturing), they removed it from later versions, that's what he meant by "legacy chips". In other words, you won't find it in an eZ80. Which one it first got removed from is a good question. Start by looking at the Z280 and see if it still had refresh. Then go forward or backward to find where it disappears.

7-bit refresh RAM was a bit of an anomaly to begin with, I don't think there would have been so many 7-bit 64K chips if it weren't for the Z80.

And the reason R was 7 bits is because of the weird 16-bit counter circuit that they used. That was documented in the Ken Shirriff blog about the Z-80. It wasn't chosen that way because someone felt that 7 bits was enough, it was because the carry to bit 7 was one of the few that could be cut. Of course this was done when 4K was a lot of memory, but still.

 

[Eudimorphodon]

I really hate to differ with the great Lee Felsenstein, but I think he might be misremembering something with these comments because what he’s saying about the Osborne-1 doesn’t seem to add up with either the documented behavior of the refresh signal or the Osborne schematics.

First off, the theoretical objection: RFSH is not periodic enough to use for screen refresh. It’s active on the M3 and M4 phases of instruction cycles, IE, the Z80 triggers a refresh when it’s busy decoding an instruction, and only then. Data read or write cycles, of which there can be an irregular number of between opcode reads, don’t trigger refresh. Which means unless you play games like the Sinclair ZX-80 and restrict yourself to running a stream of specific opcodes during the active line you can’t use it for something like video refresh counting. The Osborne does not do this.

Secondly, just read the Osborne 1 tech manual and look at the schematic. The machine doesn’t use the Z80 refresh counter at all, the theory of operations section makes it clear that the video address generator doubles as refresh. And the schematic shows likewise that the only thing done with RFSH on the board is it’s used to suppress the MREQ pulse that otherwise happens in the middle of M3/M4. (IE, any evidence of the Z80 refresh function is muted.)

And yes, thirdly, what @Bruce Tomlin said, with regard to what “legacy chips” means.

 

[Eudimorphodon]

I really hate to differ with the great Lee Felsenstein, but I think he might be misremembering something with these comments because what he’s saying about the Osborne-1 doesn’t seem to add up with either the documented behavior of the refresh signal or the Osborne schematics.

… FWIW, the Osborne 1’s video address generator *is* weird and clever in its own right (the schematic will make your head hurt and the theory of operations doesn’t do much to make it not look like black magic), but it doesn’t have anything to do with the Z80’s refresh counter. He basically made his own CRTC by mashing up TTL counters with a 6821 PIA, and it doubles as the serial baud rate generator.

 

[cj7hawk]

Or he might be remembering another machine he developed? I can't imagine the Osborne 1 was the only one.

Building a low-chip-count CRTC with minimal counters is indeed challenging.

The Osborne 1 schematics I've seen don't seem to reflect any further detection of the RFSH signal outside of mixing it inverted with MREQ so as to ensure that MREQ doesn't activate on a refresh cycle from the CPU. So if the memory request was then used as the bus arbiter, you could be reasonably confident of reading a video cycle within 4 T states, and being able to count on a read once MREQ goes high, with around 250ms to access the memory @ 4MHz after that before the next potential MREQ comes along. As long as the video circuit is waiting for MREQ to go high before reading, then this could be a legitimate bus arbitration technique for video reads.

I haven't examined the video logic closely enough to check if that's how it does it, but it's plausible to "reuse" this, and if the signal was missing, this could affect the window between memory access sufficiently to affect video - I haven't done the maths, and previously looked at this and didn't know the signals well enough to know if it was possible, but I don't know enough to prove it wouldn't work either.

If anyone else said it, I wouldn't believe it, but now I'm wondering if there's a mystery there I've never encountered before? It's not reflected in the datasheets I checked, but that doesn't exclude all possibilities. I sent a question to Lee directly to ask more.

David

 

[Eudimorphodon]

If anyone else said it, I wouldn't believe it, but now I'm wondering if there's a mystery there I've never encountered before? It's not reflected in the datasheets I checked, but that doesn't exclude all possibilities. I sent a question to Lee directly to ask more.

If the RFSH signal had just silently been deleted from the standard Z80 the chips wouldn’t work properly in any machines that uses it, either as part of an actual refresh cycle or a status pin to know you’re in an instruction cycle (another use for it), so I’m pretty sure Zilog would have told people. Absolutely guarantee you that “Legacy Chips” means what was already described above.

There is a reasonably clear explanation of how memory arbitration works in the Osborne around page 74 of the tech manual. Long and short of it is the system clock is cut into memory access windows which are shorter than either the CPU or the video system needs and the Z80 control signals are a little fudged, with the goal of trying to minimize how often it needs to pull the WAIT line. (Because ultimately you have to let video win, unless you want junk all over the screen.) it’s a clever system but it doesn’t explicitly rely on RFSH. (Although, sure, the timing windows are optimized based on knowledge of the Z80’s machine cycle, including where RFSH is.) It *would* potentially get confused if the MREQ signal that’s generated during refresh leaked out, but…

Anyway, if you think your Osborne is screwing up because you put a Z80 in it that doesn’t have RFSH this is really easy, just put an oscilloscope or logic probe on pin 28. If it’s not pulsing when the CPU is executing code then you have your answer.