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Which minicomputer architectures used "skips" to branch and had no stack?

I used the IBM ATOM (A Tiny Optimized Microcontroller) in the IBM 5224 and 5225 printers. It had a 2 level call stack. If your subroutines went more than two levels, you were toast. When I started working on this, this guy showed me this "great debug tool" (his words). You connected it to the address bus on the backplane, and set some address switches. When the processor hit that address, it would light up. I said "You never seen an ICE-85?". His reply was "Nope. What's that?"
 
Al Kossow said:
was the part only used in the printer group?
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I don't think so. It was developed in Boca Raton, and the assembler ran on MVS and VM. There were 2 used in the printers. One for control, and the other for the Head Image Generator. It was a 4 bit processor with a 12 bit address bus, bank switched to access different memory cards. It was available in a

I lost all information about the ATOM. But I still have some information on the UC0, that was used in several printers. 4214 and 3287 are the ones I worked on.
 
There are few more, less known computer systems with satisfy condition 1 or 2, for example Lockheed MAC- 16, SCC 4700, Wang 3300, Texas Instruments 980, Raytheon 703. Condition 2 is sometimes could be little different by saving return address to the special register instead of the first memory location (this is true for TI 980, Apollo Guidance Computer, Raytheon 703, this allows for using ROM e.g. core rope memory in AGC). Computers which fill those two criteria’s are usually quite similar from instruction set architecture point of view. Usually have 1-2 accumulators and 1-2 index registers (sometimes accumulators could be also index regs), only single link/carry/overflow flag and have fixed instruction format. Which consists of op code, few addressing mode bits like zero-page, index, indirect and 8/9-bit address/displacement. This style of ISA seems to be almost industry standard of late 60 and early 70.
Quite interesting sum up of this kind of ISA could be found here: Real Machines with 16, 32, and 30-bit words (quadibloc.com) and here Still More Real Machines (quadibloc.com).
 
The IBM System 360 series had no stack. A subroutine call ("Branch and Link" instruction) put the return address in one of the 16 general purpose registers and the first thing a called routine would do is save all the registers with the STM "Store Multiple" instruction into a "save area". Then to return it did a "Load Multiple" to get all the registers back, and branch via the register. There was a coding convention on which registers were used for what, and save areas would be linked together so it was possible to "unwind" the sequence of calls, somewhat like popping a stack. No skip instructions.
 
traveler_aa5 said:
I don't think so. It was developed in Boca Raton, and the assembler ran on MVS and VM. There were 2 used in the printers. One for control, and the other for the Head Image Generator. It was a 4 bit processor with a 12 bit address bus, bank switched to access different memory cards. It was available in a

I lost all information about the ATOM. But I still have some information on the UC0, that was used in several printers. 4214 and 3287 are the ones I worked on.
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I knew one of the folks that designed ATOM. it was not only used in printers but a number of adapters used in the Series/1.
 
A related tangent: Which microprocessors didn't have a stack?
The 4004 has already been mentioned.

Texas mini computers has been mentioned, and it's from them the TMS9900 microprocessor family inherited not having a stack. They rather use the somewhat weird mechanism of having 16 registers stored in RAM rather than inside the microprocessor, and a register pointing to where in RAM these registers are stored. They have two types of subroutine calls. One switches both program counter and where the registers are located, while storing the old PC and register locations (and status register) in three of the "new" registers. The other type just stores PC in one of the registers, and thus you return by doing an indirect jump to where that register points.

The 1802 hasn't been mentioned yet in this thread. It has 16 16-bit registers, and a 4-bit register selecting which of the 16 16-bit registers is used as the program counter. Subroutines are called by changing which register is the program counter, and returning is obviously done by changing the program counter back to the register it used to use.


Another question: Which processors did have multi byte NOPs, or something of a similar effect?
The 6502 has the BIT instruction that just loads bit 6 and 7 of the operand into two of the status register (and maybe sets the zero flag depending on if the operand is zero or not, can't remember). This might be useful as is, but it can also be used as a 2/3 byte NOP. In particular you can have a routine with two entry points. One that executes a bunch of code, and another that executes one or two bytes of code and then continues in the middle of the routine. Normally this would be achieved with a jump/branch, but on the 6502 you can have a BIT instruction with a one or two byte operand right before the second entry point, and that one or two byte operand would form actual code that would only run when entering into the second entry point. IIRC Microsoft 6502 basic uses this.
 
The Harris/Intersil 6100 counts, being an LSI PDP-8, but weirdly enough the 6120 actually adds a rudimentary stack capability (that I'm not sure anybody ever used...)
 
Data General NOVA computers, had skips and no dedicated stack pointer. You could load/store indirectly off registers or memory, increment/decrement simultaneously. (Indirect references through low memory, I think 0004x octal, would increment or decrement, depending. Every newbie forgot this and found out the hard way, they made for poor subroutine return address storage. We called those locations auto-Xcrement fo obvious punny reasons).
 
tomjennings said:
Data General NOVA computers, had skips and no dedicated stack pointer. You could load/store indirectly off registers or memory, increment/decrement simultaneously. (Indirect references through low memory, I think 0004x octal, would increment or decrement, depending. Every newbie forgot this and found out the hard way, they made for poor subroutine return address storage. We called those locations auto-Xcrement fo obvious punny reasons).
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Later microNova added a stack pointer.
 
Yeah, that's a feature carried over from the PDP-8. Fairly handy if you're doing linear array access, fairly useless otherwise. Now I'm curious if anybody else implemented such a feature on other contemporary systems, or if that's specifically a de Castro-ism...
 
commodorejohn said:
Yeah, that's a feature carried over from the PDP-8. Fairly handy if you're doing linear array access, fairly useless otherwise. Now I'm curious if anybody else implemented such a feature on other contemporary systems, or if that's specifically a de Castro-ism...
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Dedicated stack pointers began to be "required" with compilers, for argument passing formalities. In the 60's many minis did not have stack pointers or other register-relative address calcs (eg. BP in x86) (though I'm sure some did). Personally, Varian 620/622's and A, B, X regs where X was specifically an address (index) register, again no stack. It accommodated subroutine calls with JMPM, "jump and mark", eg. call subroutine at address SUBR by (1) storing the the the return address at SUBR and (2) executing the instruction at SUBR+1. Return was by jumping indirect, eg. "@ SUBR".

This was not uncommon.

(The Nova minis also allowed JMP @location, where location was a named memory location; the jump was not "jump location" but "jump to contents of location". This was called indirect addressing by DG. Further, if the MSB of the indirect address, was true, *that address" was again used indirectly; it was actually possible to create an endless loop of indirect address references which would "loop" within the ALU fetch machine. You could often literally hear this happen; the switcher power supplies operated in the audio range, and the sound of JUMP 0 where 0 contained a 0 (which is a JUMP instruction) and indirect loops created a non-varying current consumption and the P.S. sound became very distinct.)

Rich (BB code): 
   ...
   CALL SUBR
   ...
 
 
 
SUBR:
   DATAWORD 0         (* storage word for return address *)
   instruction
   instruction
   ...
   JMP @ SUBR          (* return from subroutine; jump to address stored at SUBR *)

Indirect memory addressing (jump to *contents of* address) is one of those architectural features that has disappeared.
 
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The "auto-increment" feature on the PDP-8 was taking advantage of a quirk in core memory. Reading a location had a side effect of clear it to zero, so it had to be rewritten each time. This was an opportunity to increment the value without the cost of another memory cycle.
 
tomjennings said:
(The Nova minis also allowed JMP @location, where location was a named memory location; the jump was not "jump location" but "jump to contents of location". This was called indirect addressing by DG. Further, if the MSB of the indirect address, was true, *that address" was again used indirectly; it was actually possible to create an endless loop of indirect address references which would "loop" within the ALU fetch machine. You could often literally hear this happen; the switcher power supplies operated in the audio range, and the sound of JUMP 0 where 0 contained a 0 (which is a JUMP instruction) and indirect loops created a non-varying current consumption and the P.S. sound became very distinct.)

Rich (BB code): 
   ...
   CALL SUBR
   ...
 
 
 
SUBR:
   DATAWORD 0         (* storage word for return address *)
   instruction
   instruction
   ...
   JMP @ SUBR          (* return from subroutine; jump to address stored at SUBR *)

Indirect memory addressing (jump to *contents of* address) is one of those architectural features that has disappeared.
Click to expand...
The Nova also had indirect Load/Store. One problem with indirect addressing was the address had to be +/- 127 words from the current instruction, as it took the lower byte as the offset. The assembler had a instruction ".LPOOL" where indirect addresses could be stored. Just make sure you don't start executing the code.:)
 
As I recall, the PDP-10 had both conditional SKIP instructions, conditional JUMP instructions, and a stack.
 
Going the other way, what was the first machine with a real hardware stack?
 
I suppose I was thinking about a modern stack pointer in main memory.
 
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