saipan59
Experienced Member
Hi All,
There is another thread discussing the "T11 board" that I designed. A total of 10 boards were fabbed.
Fellow forum-reader Mitch has prompted me to consider getting another batch of PCBs.
They would be the "V1.1" boards, which fix a couple of minor errata. The main difference is that V1.1 allows a 4-position DIP switch to be used in place of the jumpers (jumpers still work too).
If I am going to be doing the packing and shipping (which I really don't like), then the deal is this:
- Six boards will be fabbed. Mitch gets two, I get one. There are two other folks that get "first dibs" on boards 4 and 5, because they wanted to get a board from the 1st batch. The 6th board would be available.
- PCB cost would be $24.40 each, plus shipping. Shipping is $4 in the US, about $10 for Europe.
- EEPROMs pre-burned with the Forth image are $3.25 each, limit two. I would need to buy a new batch of EEPROM chips. $3.25 each is my actual cost from a US dealer.
- I can provide an MC6850 with each board, the same as the first batch.
- No other parts provided by me.
Another approach:
If there is someone that has the time and interest to handle the logistics, then we could do it like this:
- That other person does the PCB order; for whatever quantity is needed.
- I buy and program the required number of EEPROMs for everybody, and send the whole batch to the Logistics person for re-distribution. We settle up on the cost of the EE's vs the cost of my one board.
- The Logistics person could consider acquiring other needed parts for re-distribution. Things like SRAM, crystals, 74HCT174, etc.
- I become a "customer" for one of the new PCBs.
- I will sell my original "V1.0" board, assembled and working, including T11 chip, for $75 plus shipping. I'll build myself a new V1.1 board. If nobody wants it at this price, then I'll keep it.
Please reply to this thread if you're interested in the above proposals.
Thanks! Pete
Some details about the board:
-----
This board has the following features:
-----
DEC T11 (DC310) microprocessor
8KB of EEPROM at address 40000.
8KB of static RAM at address 0.
T11 configured for "8-bit static" mode.
Each 8KB bank of memory space is decoded.
Upper 8KB bank is decoded into 1KB banks.
EEPROM can be hot-swapped.
MC6850 UART at address 160000.
Six bits of general-purpose output at 162000.
Four bits of general-purpose input at 164000.
Optional LED on P1_0 output port.
I have a stand-alone FigForth V1.3 image that runs on this platform.
-----
Versions:
-----
V1.0
Original version; 10 boards fabbed May/June 2015.
V1.1
(Not fabbed yet).
Added J9, so that a 4-position DIP switch can be used at J2.
Added J10, to bring out the remaining 4 T11 signals.
-----
ERRATA:
-----
In the layout, power connector J1 is not aligned on a 0.1" grid with the
other connectors. See V1.1 for fix.
Connector J2 has 0.1" spacing, which is good for jumpers, but I had planned
to support a 4-position DIP switch also. See V1.1 for fix.
Power connector J1 has no marking to indicate "+" and "-", although
the C15 "+" marking is nearby. See V1.1 for fix.
U9 should have additional logic on the CS, such that it is only active on
a Write. Since the T11 precedes a write with a read, U9's output will pulse
high just before being written low. This effect is only visible if the U9 bit
is already low, and the code writes it low again.
The MC6850 "E" signal is not being driven properly. Per the datasheet, the
timing should be: CS goes low; E goes high at least 40nS later (68B50) or
80nS later (6850); E stays high for at least 220nS (68B50) or 450nS (6850);
CS stays low for at least another 10nS. In this design, E is driven directly
from COUT. It meets the requirements, except that another COUT pulse starts
just before CS goes high.
The MC6850 UART misbehaves if U9 is installed. The problem seems to be related
to bus loading, but it's unclear why it happens. It's possible that the problem
is related to the E timing issue in the note above. Using a 74HCT174 part for
U9 avoids the problem.
-----
Board assembly notes:
-----
Refer to the mechanical image for location/placement of parts.
U7 has some space around it in the layout to allow a large ZIF socket to
be used, but only if J6 and J7 are not installed.
Note that U4, U5, U6, and U7 are "backwards" in the layout, relative to
other chips.
Recommend using socket pins for X1, C2, and C3, so that you can easily
experiment with different values.
Resistor R1 needs to be 1K, 1% tolerance, per the T11 spec.
If LED D1 is installed, the cathode is the square pad.
V1.1 only: A 4-position DIP switch can be used at J2.
-----
Schematic Page 1:
-----
Caps C2 and C3 need to be chosen to match crystal X1. 25-35 pF should work.
Max xtal freq is 7.5 Mhz, but you may want to choose a value that
allows a standard baud rate, such as 2.4576 Mhz. With a standard MC6850
UART, the max xtal freq is 2 Mhz.
-----
Schematic Page 2:
-----
Inputs to U3 can be modified (with etch cuts) to change startup config.
-----
Schematic Page 3:
-----
EEPROM U7 can be write-protected. See EEWE signal, and page 5.
U7's Vcc power can be interrupted to allow hot-swap.
-----
Schematic Page 4:
-----
U10 is configured to prevent it from driving the bus on
a Write transaction.
U10 pins 11 and 12 are unused.
UART U8 can get its baud clock from the T11, or from an external
source (see page 5).
With MC6850, max T11 xtal freq is 2 Mhz.
With MC68A50, max T11 xtal freq is 3 Mhz.
With MC68B50, max T11 xtal freq is 4 Mhz.
With UART configured (in software) with divide-by-64 clock, baud rates are:
1.8432 Mhz xtal --> 14400 baud (works with any MC6850)
2.4576 Mhz xtal --> 19200 baud (requires MC68A50 or MC68B50)
3.6864 Mhz xtal --> 28800 baud (requires MC68B50)
7.3728 Mhz xtal --> 57600 baud (too fast for MC68B50, but may work anyway??)
-----
Schematic Page 5:
-----
J2 functions:
Pins 1-2 connect the T11 COUT as the UART baud clock (default ON).
Pins 3-4 assert DMR, causing the T11 to go into a DMA transaction indefinitely (default OFF).
Pins 5-6 enable writing of the EEPROM (default OFF).
Pins 7-8 enable Vcc power to the EEPROM (default ON).
-----
Chip selections:
-----
To reduce board current consumption a bit, use 74HCT-series parts where possible.
A standard MC6850 is a 1 Mhz part. This refers to the speed on the "E" pin, not
the baud clock. The "E" pin is driven by COUT, which is half of the T11 crystal
freq. SO, 2 Mhz is the fastest crystal to use with the MC6850. The 68A50 is a
1.5 Mhz part, while the 68B50 is 2 Mhz.
If using an HCT part for U9, be aware that the output drive current is officially
limited to 4 mA. Actual current can be higher, if you don't care about V level.
-----
EEPROM hot-swap:
-----
Note: This process may not be 100% reliable. I only use it to "clone" an EE chip
using the SAVE word that I added in Forth. It would be smart to add a word
that calculates a checksum on the EE contents, then you can be confident that
everything worked in the cloning process.
Steps:
Use a ZIF socket for U7.
Assume that code runs entirely from RAM after boot-up.
Board is initially powered and running.
Install the 3-4 jumper, putting the T11 in a DMA transaction.
Remove the 1-2 jumper, to stop the baud clock to the UART (not sure if
this is necessary, but it seems to help reliability).
Remove the 7-8 jumper, which turns off power to the EEPROM.
Replace the chip at U7 (ZIF socket).
Install the 7-8 jumper, to power-up the new EE chip.
Install the 1-2 jumper.
Remove the 3-4 jumper, releasing the DMA transaction.
-----
Stand-alone FigForth V1.3 image:
-----
The console is the MC6850 UART at address 160000.
The MC6850 is configured by the Forth startup code with the divide-by-64 clock option,
so that it can run directly from the T11's COUT signal.
There is no disk support, and no Forth screens.
On startup, the EE image at 40000 copies itself to RAM at 0-17777, then resumes
execution in RAM.
I added a SAVE word that copies all of RAM to EEPROM. It runs for about 90 seconds.
The implementation looks like this:
// Delay about 10 mS with a 2 Mhz clock.
: DEL5 5 0 DO 10 10 * DROP LOOP ;
// Save the complete system to EEPROM. Executes in about 90 seconds.
: SAVE 8192 0 DO I DUP 16384 + 1 CMOVE DEL5 LOOP ;
-----
To build a Forth image that runs on startup, and does not require any serial interaction:
-----
Create a MAIN word that you want to execute on power-up. MAIN can call any other words
that have been declared:
: MAIN BEGIN <do stuff> AGAIN ; // example
Poke MAIN's CFA into the SPACE location inside the ABORT definition. This will cause
MAIN to execute on startup, before any UART activity. Type this Forth command:
' MAIN CFA 4292 !
Save the system image from RAM to EEPROM (install the "EEWE" jumper to write-enable the EE):
SAVE
If you power-cycle the T11, your MAIN word should now run automatically. Since MAIN runs
before using the UART, the UART is not required at run-time.
Before you do any of this, it would be smart to have a copy of your known-good Forth chip,
in case you make a mistake...
There is another thread discussing the "T11 board" that I designed. A total of 10 boards were fabbed.
Fellow forum-reader Mitch has prompted me to consider getting another batch of PCBs.
They would be the "V1.1" boards, which fix a couple of minor errata. The main difference is that V1.1 allows a 4-position DIP switch to be used in place of the jumpers (jumpers still work too).
If I am going to be doing the packing and shipping (which I really don't like), then the deal is this:
- Six boards will be fabbed. Mitch gets two, I get one. There are two other folks that get "first dibs" on boards 4 and 5, because they wanted to get a board from the 1st batch. The 6th board would be available.
- PCB cost would be $24.40 each, plus shipping. Shipping is $4 in the US, about $10 for Europe.
- EEPROMs pre-burned with the Forth image are $3.25 each, limit two. I would need to buy a new batch of EEPROM chips. $3.25 each is my actual cost from a US dealer.
- I can provide an MC6850 with each board, the same as the first batch.
- No other parts provided by me.
Another approach:
If there is someone that has the time and interest to handle the logistics, then we could do it like this:
- That other person does the PCB order; for whatever quantity is needed.
- I buy and program the required number of EEPROMs for everybody, and send the whole batch to the Logistics person for re-distribution. We settle up on the cost of the EE's vs the cost of my one board.
- The Logistics person could consider acquiring other needed parts for re-distribution. Things like SRAM, crystals, 74HCT174, etc.
- I become a "customer" for one of the new PCBs.
- I will sell my original "V1.0" board, assembled and working, including T11 chip, for $75 plus shipping. I'll build myself a new V1.1 board. If nobody wants it at this price, then I'll keep it.
Please reply to this thread if you're interested in the above proposals.
Thanks! Pete
Some details about the board:
-----
This board has the following features:
-----
DEC T11 (DC310) microprocessor
8KB of EEPROM at address 40000.
8KB of static RAM at address 0.
T11 configured for "8-bit static" mode.
Each 8KB bank of memory space is decoded.
Upper 8KB bank is decoded into 1KB banks.
EEPROM can be hot-swapped.
MC6850 UART at address 160000.
Six bits of general-purpose output at 162000.
Four bits of general-purpose input at 164000.
Optional LED on P1_0 output port.
I have a stand-alone FigForth V1.3 image that runs on this platform.
-----
Versions:
-----
V1.0
Original version; 10 boards fabbed May/June 2015.
V1.1
(Not fabbed yet).
Added J9, so that a 4-position DIP switch can be used at J2.
Added J10, to bring out the remaining 4 T11 signals.
-----
ERRATA:
-----
In the layout, power connector J1 is not aligned on a 0.1" grid with the
other connectors. See V1.1 for fix.
Connector J2 has 0.1" spacing, which is good for jumpers, but I had planned
to support a 4-position DIP switch also. See V1.1 for fix.
Power connector J1 has no marking to indicate "+" and "-", although
the C15 "+" marking is nearby. See V1.1 for fix.
U9 should have additional logic on the CS, such that it is only active on
a Write. Since the T11 precedes a write with a read, U9's output will pulse
high just before being written low. This effect is only visible if the U9 bit
is already low, and the code writes it low again.
The MC6850 "E" signal is not being driven properly. Per the datasheet, the
timing should be: CS goes low; E goes high at least 40nS later (68B50) or
80nS later (6850); E stays high for at least 220nS (68B50) or 450nS (6850);
CS stays low for at least another 10nS. In this design, E is driven directly
from COUT. It meets the requirements, except that another COUT pulse starts
just before CS goes high.
The MC6850 UART misbehaves if U9 is installed. The problem seems to be related
to bus loading, but it's unclear why it happens. It's possible that the problem
is related to the E timing issue in the note above. Using a 74HCT174 part for
U9 avoids the problem.
-----
Board assembly notes:
-----
Refer to the mechanical image for location/placement of parts.
U7 has some space around it in the layout to allow a large ZIF socket to
be used, but only if J6 and J7 are not installed.
Note that U4, U5, U6, and U7 are "backwards" in the layout, relative to
other chips.
Recommend using socket pins for X1, C2, and C3, so that you can easily
experiment with different values.
Resistor R1 needs to be 1K, 1% tolerance, per the T11 spec.
If LED D1 is installed, the cathode is the square pad.
V1.1 only: A 4-position DIP switch can be used at J2.
-----
Schematic Page 1:
-----
Caps C2 and C3 need to be chosen to match crystal X1. 25-35 pF should work.
Max xtal freq is 7.5 Mhz, but you may want to choose a value that
allows a standard baud rate, such as 2.4576 Mhz. With a standard MC6850
UART, the max xtal freq is 2 Mhz.
-----
Schematic Page 2:
-----
Inputs to U3 can be modified (with etch cuts) to change startup config.
-----
Schematic Page 3:
-----
EEPROM U7 can be write-protected. See EEWE signal, and page 5.
U7's Vcc power can be interrupted to allow hot-swap.
-----
Schematic Page 4:
-----
U10 is configured to prevent it from driving the bus on
a Write transaction.
U10 pins 11 and 12 are unused.
UART U8 can get its baud clock from the T11, or from an external
source (see page 5).
With MC6850, max T11 xtal freq is 2 Mhz.
With MC68A50, max T11 xtal freq is 3 Mhz.
With MC68B50, max T11 xtal freq is 4 Mhz.
With UART configured (in software) with divide-by-64 clock, baud rates are:
1.8432 Mhz xtal --> 14400 baud (works with any MC6850)
2.4576 Mhz xtal --> 19200 baud (requires MC68A50 or MC68B50)
3.6864 Mhz xtal --> 28800 baud (requires MC68B50)
7.3728 Mhz xtal --> 57600 baud (too fast for MC68B50, but may work anyway??)
-----
Schematic Page 5:
-----
J2 functions:
Pins 1-2 connect the T11 COUT as the UART baud clock (default ON).
Pins 3-4 assert DMR, causing the T11 to go into a DMA transaction indefinitely (default OFF).
Pins 5-6 enable writing of the EEPROM (default OFF).
Pins 7-8 enable Vcc power to the EEPROM (default ON).
-----
Chip selections:
-----
To reduce board current consumption a bit, use 74HCT-series parts where possible.
A standard MC6850 is a 1 Mhz part. This refers to the speed on the "E" pin, not
the baud clock. The "E" pin is driven by COUT, which is half of the T11 crystal
freq. SO, 2 Mhz is the fastest crystal to use with the MC6850. The 68A50 is a
1.5 Mhz part, while the 68B50 is 2 Mhz.
If using an HCT part for U9, be aware that the output drive current is officially
limited to 4 mA. Actual current can be higher, if you don't care about V level.
-----
EEPROM hot-swap:
-----
Note: This process may not be 100% reliable. I only use it to "clone" an EE chip
using the SAVE word that I added in Forth. It would be smart to add a word
that calculates a checksum on the EE contents, then you can be confident that
everything worked in the cloning process.
Steps:
Use a ZIF socket for U7.
Assume that code runs entirely from RAM after boot-up.
Board is initially powered and running.
Install the 3-4 jumper, putting the T11 in a DMA transaction.
Remove the 1-2 jumper, to stop the baud clock to the UART (not sure if
this is necessary, but it seems to help reliability).
Remove the 7-8 jumper, which turns off power to the EEPROM.
Replace the chip at U7 (ZIF socket).
Install the 7-8 jumper, to power-up the new EE chip.
Install the 1-2 jumper.
Remove the 3-4 jumper, releasing the DMA transaction.
-----
Stand-alone FigForth V1.3 image:
-----
The console is the MC6850 UART at address 160000.
The MC6850 is configured by the Forth startup code with the divide-by-64 clock option,
so that it can run directly from the T11's COUT signal.
There is no disk support, and no Forth screens.
On startup, the EE image at 40000 copies itself to RAM at 0-17777, then resumes
execution in RAM.
I added a SAVE word that copies all of RAM to EEPROM. It runs for about 90 seconds.
The implementation looks like this:
// Delay about 10 mS with a 2 Mhz clock.
: DEL5 5 0 DO 10 10 * DROP LOOP ;
// Save the complete system to EEPROM. Executes in about 90 seconds.
: SAVE 8192 0 DO I DUP 16384 + 1 CMOVE DEL5 LOOP ;
-----
To build a Forth image that runs on startup, and does not require any serial interaction:
-----
Create a MAIN word that you want to execute on power-up. MAIN can call any other words
that have been declared:
: MAIN BEGIN <do stuff> AGAIN ; // example
Poke MAIN's CFA into the SPACE location inside the ABORT definition. This will cause
MAIN to execute on startup, before any UART activity. Type this Forth command:
' MAIN CFA 4292 !
Save the system image from RAM to EEPROM (install the "EEWE" jumper to write-enable the EE):
SAVE
If you power-cycle the T11, your MAIN word should now run automatically. Since MAIN runs
before using the UART, the UART is not required at run-time.
Before you do any of this, it would be smart to have a copy of your known-good Forth chip,
in case you make a mistake...