At this point I have a general or "block diagram" understanding; the XT bus has 20 address lines = 1,048,576 separate addresses; of these some are memory locations, some ports, the BIOS etc.
IBM PC/XT has a separate (from memory) I/O space. The 8088 CPU generates 16-bit address (65536 different addresses). But XT motherboard and various extension cards tend to decode only lower 10-bit of address, so effectively the range is reduced to 1024 addresses - that is from 000h to 3FFh. Lower 512 addresses used (or reserved) for peripherals on the motherboard. So effectively extension cards can use 200h to 3FFh. There is a lot of reference material on how these ports are allocated. You can start
here.
Memory is indeed uses 20-bit address, which gives 1 MiB of memory space. Lower 640 KiB (00000h to 9FFFFh) are used by RAM (conventional memory), next there is a block which normally used by display cards (0A0000h to 0BFFFFh), next there is an area that used by extension cards either for BIOS extension ROMs, or for RAM (e.g. EMS window, or UMBs), finally last 64 KiB (0F0000h to 0FFFFFh) are allocated for BIOS and ROM BASIC.
The Intel 8080 and 8237 can communicate with these addresses. Devices keep synchronized with one another by means of the system clock and signal their need to use the bus with signal voltages on control lines.
I am sure you meant Intel 808
8. And yes both CPU and DMAC can communicate with memory and I/O devices, except that DMAC can only generate 16-bit memory address, so there is a 4x4-bit page register that provides upper 4-bit of address. Also DMAC does not normally generate I/O addresses - it uses /DACK signals to select I/O devices instead. System clock is not used to synchronize the devices, and XT bus is an asynchronous bus. There are a few signals that control data transfer (/MEMR, /MEMW, /IOR, /IOW).
I'd like to bring my knowledge to the level of understanding how devices communicate, why they occupy the addresses that they do and how the system differentiates between them. Obviously the wrong signal sent to the wrong address or at the wrong time could be fatal, so how is this avoided?
On XT bus only CPU and DMAC can initiate memory or I/O transactions (as opposed to real AT ISA bus, which has some bus mastering support). Basically the CPU or DMAC puts the address it wants to read from or write to on the address bus, and in case of the write the CPU will also output the data byte on the data bus. Next one of the control signals I've mentioned above activated (that is switched to LOW level). That actually initiates the transaction.
DMA transfer is a little bit more complicated: IBM PC/XT supports only memory to I/O and I/O to memory DMA (no memory to memory). The DMAC provides the memory address, and in case of memory to I/O it activates /MEMR, one of /DACK signals, and /IOW. In case of I/O to memory it activates /IOR, /DACK, and /MEMW. So that the data flows directly between memory and I/O.
Additionally IBM PC/XT has a bus arbitration circuit, which makes sure that CPU is not accessing the bus during DMA cycles.
Your another question has to do with address decode. Each device (memory, or I/O) normally has a chip select input (/CS, or /CE), and there are address decoders (or comparators) that have their inputs connected to the address bus, and outputs to these chip select inputs. So basically a decoder always try to decode the address present on address bus, and if that address matches the device (or memory) address, it would select the chip. That doesn't initiate the transaction yet, but just select the device used for the transaction.
My answers above are oversimplified, for example they don't take timing into consideration.
Wrong signal to wrong address: I don't really understand what is "wrong signal", but there are a few possibilities:
- Non existent address being read or written - probably nothing bad will happen, except that the read value would be garbage
- Multiple devices are set to decode the same address - in case of write (to device), both of devices will get the data. In case of read - it would be bus contention. Normally it shouldn't damage anything (not enough time to do any damage), but potentially it could
- Device is being written a garbage/incorrect value or command. It really depends what device we are talking about, and what is that incorrect command. The answer could vary from no damage at all to a corrupted disk, or a damaged monitor...
It looks that you don't really understand how Intel 8088 CPU works, so I'd recommend reading a college book on it, e.g.
The 8086/8088 Family: Designing, Programming and Interfacing. That should be more useful than reading a reference manual (that normally assumes some level of familiarity with CPU architecture).
