Recent content by pearce_jj

Re main battery - the mAh capacity really doesn't matter - it just defines the run-time. More mAh will give more run time. Provided it's a 4-cell NiCd type it should work fine, albeit with a life expectancy of only a few years. Re internal battery - I soldered some wires to the terminals of...

D-cell type are still available as used in some home alarm systems, for example: https://www.fireprotectionshop.co.uk/p/4.8v-emergency-lighting-battery-pack-side-by-side.html I've used a radio-control model 4.8V NiMH battery - with appropriate connection adapter - but I found that although the...

At least on 5160, it will need to use slot 8 or have a physical connection to the ROM socket(s). I’ve documented why here: https://www.lo-tech.co.uk/understanding-pcxt-slot-8/ I don’t know about other systems.

One challenge might be that the system board buffers make placement difficult. On 5160 for example, we cannot DMA from slot 8 but I think we also cannot present Fxxx except from slot 8 (or the ROM sockets of course).

The shadow function can potentially improve performance only on machines with 16-bit memory bus - 8086, v30, and 286 machines basically.

In my view it would be interesting to look at the file system capabilities of these chips themselves, since regardless of how tiny and weak these MCUs are, they surely must be faster, probably significantly faster, than an 8088.

I've not costed these yet as the 1st draft designs are only just complete. The intention is to run a short batch of engineering samples in the first instance to test the market. I purchased two CH376S based boards (several years apart) and, perhaps interestingly, both only return 08h...

Both the single socket and the new two socket version will be 4 layer boards and entirely SMD based. Bare PCBs account for a tiny minority of demand now so these are being designed for short run production.

Quick first look at what I've been working on - dual socket USB based storage adapter. One internal, one external. The component count is quite high and this might make it a little expensive to produce, but I will also run a rev2 of the single-socket board as well (with the port mapping corrected).

The XTIDE UB runs with interrupts enabled (see Int13h.asm): 95 Int13h_DiskFunctionsHandler: 96 %ifndef RELOCATE_INT13H_STACK 97 sti ; Enable interrupts

Maybe an answer is to have the BIOS not take memory, but implement a function call allowing it to do so? So the feature can be enabled at run time if required.

Data port always 260h. Command port 261h for standard and 262h for fast.

The REP INSW mod @Malc pertains only to 186/v20 CPUs. Hence if it’s actually an XT, with 8088 CPU, it won’t work as it stands. It can be modified along the lines of my post a few days back, but a little bit more work to do.

@Malc - forgive me, it's hard to keep track of testing configurations. Which CPU and board is the latest BIOS test (4MB copy in 1m55s) done with? @Hak Foo - the 8086 sector transfer code can be improved by unrolling the loop. e.g., replacing this: MOV CX, AX ;SET CX TO NUMBER OF BYTES...

Re INSW. The low byte is read from port n and the high byte from port n+1. When reading a word from an 8-bit expansion card, there are physically two ISA bus cycles back to back generated from each instruction. This is how the Lo-tech card is able to achieve a performance gain - by mapping A0...