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I went back to the initial programming of the CPLDs and restored the ICs used in the initial testing. After doing this I was able to get the system to POST again. I started a debugging log where I am logging every change and then do some power cycle tests to record how many cycles are needed...

I have done a lot of testing, and expanded my list of things to look at. Last night I was even unable to get the CPU to run properly anymore. I am retracing my steps and restoring the initial situation. I can't exclude that there may be some marginal problem in one of the CPLDs even since they...

I have made a new XT-IDE AT configuration and tested with the primary and secondary IDE ports. It appears to work properly now. I can see a harddisk attached to the secondary, and I can see partition information in FDISK. I tested with a NTFS drive but I will format one later on. It seems that...

Indeed, I will test other BIOS versions yet. I will add it to my list. However the MR BIOS is the one BIOS in which I have the most faith. There are of course others, thanks Alvaro for the URL I will check it out. Today I tested with power-on reset enabled in the CPLDs and with disabling race...

A few more things resulting from my work so far. Possibly the DMA clock frequency was no issue and probably when the power cycle problem is resolved I will return the DMA controllers to the previous 4,77 Mhz operation or even the specified 5Mhz for performance reasons. If I can get DMA to work...

Hi Alvaro, It is great to hear from you! And thanks for your compliments, I appreciate that. Getting to this first prototype is a very important milestone for me to recreate the amazing AT design. I have a lot of appreciation and respect for the IBM AT designs and concept by Don Estridge...

Apparently the problem of needing many power cycles is not gone yet. There was some fluke which caused a few sooner stable cycles but later the problem returned and was the same. Also when test exchanging the load capacitors on the 82284 clock generator which occasionally caused the clock to...

I have done more testing and I have found one of the factors in the problem where I need many power cycles to get the CPU to stay active. I now have a correct power cycle happening after powering off and on about two or three times which is a huge improvement, previously I needed more than 20...

Hi rask, Yes, it would require desoldering the PAL chip from the board. Desoldering anything from a PCB, and even working with it and handling it, connecting, disconnecting etc. all carries risks. This is always the own and sole responsibility of any person who uses the information in this...

Some photos and screenshots to share the happy news And I forgot to mention, the onboard primary IDE interface and floppy drive interface are also fully functional. The secondary IDE I still need to test, I need to create a new XT-IDE AT version ROM which includes the secondary interface. Then...

I have done a lot more testing. I took out more ICs on the 5170 mainboard and soldered in more sockets for testing. I tested all my keyboard controllers, they all work on the 5170. Next I proceeded to exchange all the 74ALS573 latches on the 5170 for sockets and tested with 74HCT573, which...

It appears that - if - the CPU can keep running, which needs a number of power cycles and resets to get a good startup of the CPU, more stuff will happen and get detected etc. It doesn't appear to be a problem detected by the POST which stops the system from POSTing further persé, but rather...

Hi Ruud, Thanks for the compliment, I am working hard to narrow down the problem, so far it's not too clear what the cause is yet. I do have a ATI Small Wonder card and monochrome CRT, I was not sure if it is going to work before so I didn't test much with it yet. Apparently I need many resets...

Hi mogwaay, Thanks for the encouragements, it's much appreciated and great to see your post here. I was also surprised that I got some screens working already at this phase since I have made so many changes in one go to reach this design step. I know I should have done the "inbetween" steps...

I have fully assembled the mainboard and soldered 1MB of SRAM onto the memory card. Of my 10 CPLDs only 4 are able to erase and program. Possibly the JTAG pins are disabled on the other CPLDs or they are defective. To re-enable the JTAG pins would be requiring a special programmer to do this as...

Hi Frank4545, Besides checking what was already said in this thread, I would like to add that you need to check RN1 since you mentioned a crack. You can measure the opposing pins with eachother with your meter in ohms mode which should show around 30 ohms for each of the 8 resistors inside RN1...

A small update to the work on the project. I have done a lot of work on the mainboard, the work was made more difficult by a shortage of components which I had to desolder from other mainboards. This posed another complication because those mainboards were faulty and unstable so I needed to...

Hi djfitzgerald, I read your descriptions and it sounds like a problem with your serial mouse which I have experienced with my prototype designs while testing them. Previously I built several XT revisions and I came across the same problem you have been experiencing several times. Lately I am...

Yes, this one is definitely the best I have tested so far. These days I am doing a lot of desoldering. This hand unit Hakko is actually a lot cheaper compared to other models because it is smaller and more simple in construction. It's really good construction quality, great materials and has a...

I just received the PCBs, they look in reasonable quality and arrived undamaged as far as I can see. And they remained straight as well and not warped due to shrink wrapping, so it's looking good so far. I will start the assembly work now, I am still waiting for the PLCC 84 pin sockets to...