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small 68000 SBC

N

norwestrzh

Experienced Member
Joined
Jan 11, 2021
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169
Location
mount vernon, wa
Here's a small homebrew 68000. It has 2 MB of SRAM and 128k of EEPROM. Runs at 25 MHz. Two serial ports at 38.4k baud via a 68681 DUART. It has a compact flash interface via a Toshiba 82C55A. Currently running CP/M 68k (v1.3) with sixteen 8 MB "disk drives" on the compact flash.
 

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Ruud said:
Do you have plans to release the schematics, Gerber files, code, etc?
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I suppose that I could do that .... at least the Gerbers. But how? I used to have a "user Web site" on Google where I posted details of a lot of my projects (www.hanscom.us), but several years ago Google "upgraded" the format of their sites and completely destroyed their usefulness for distributing information like that. *frown* There's direct contact information (I believe) in what's left of that Google site. If you drop me an e-mail at that address, I can send you the .zip file that was used to produce the PCB at JLCPCB. I also have no problem releasing the code (firmware and compact flash image), but that will take quite a bit more effort on my part to pull it together, so maybe further on down the road? And again, how would I do that? Much larger files.

I must stress that I'm not able to provide a lot of support for a project like this. I'm just an amateur.

Roger
 
GitHub is probably the most typical place to host projects like this. I’d love to check out the circuit design and potentially build one to mess with. Nice work. It’s a great accomplishment to design something like this from scratch!
 
As a follow-up to my post above, I used the same basic design but with a FreeScale MC68SEC000FU20 CPU. I find soldering TQFP .8mm parts very <ahem> challenging, but my friend is a soldering whiz. He provided me with the CPU on an adapter board (thanks Johan!) that I used as sort of a daughter board on the main PCB. I just got done building the board, and find that it will run both a monitor and CP/M 68K at 32 MHz very nicely!! I find that quite amazing for a simple through hole 2-layer PCB. My friend told me that he was able to "free run" the CPU at 50 MHz. I tried to run the PCB at 40 MHz, and the monitor will run, but it can't boot up CP/M 68k. I suspect it is at the "ragged edge" of the timing of the support circuitry. I'd like to try to run it at 36 or 38, but I don't have any oscillators. I'll have to order some.

WRT the suggestions above that I put this design on GitHub, I'd rather not do that. If anybody wants to experiment with either the PLCC board (above) or the 68SEC000 board, just message me and I'll respond with the zip file used to fab. the board. That way you can use the fab. house of your choice. I used JLCPCB.

Roger
 

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norwestrzh said:
I suppose that I could do that .... at least the Gerbers. But how? I used to have a "user Web site" on Google where I posted details of a lot of my projects (www.hanscom.us), but several years ago Google "upgraded" the format of their sites and completely destroyed their usefulness for distributing information like that. *frown*
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I may be a bit old-school here, but to my mind there's nothing better than a big ol' "pile of files" for distributing information about projects like this. Writeups go into text files (in Markdown format in .md files if you're feeling particularly energetic—but note that these are still text files you can read in any editor!), pictures go into .jpg or .png files or whatever, and the rest is whatever it is. Using subdirectories is helpful, but not required.

Put this all in a Git repo and you have an easy way of copying it back and forth, including any changes you make to it as time goes on. Put that repo up on one of the many Git hosting services, (GitHub.com, GitLab.com, GitLab set up on your own server, a zillion other options, and now others can see it and even offer improvements and fixes. You can even just drop a Git repo onto any old HTTP server, run git-update-server-info in it, and now people can git clone from that URL.)
 
>> I used the same basic design but with a FreeScale MC68SEC000FU20 CPU.

My friend, Johan, suggested replacing the 74LS chips on the FreeScale MC68SEC000FU20 version of this board with HC in an effort to get more speed out of it. Mine (with 74LS) was running 68K CP/M at 32 MHz. I followed his suggestion and got an additional 4 MHz of performance. It now runs 68K CP/M at 36 MHz. It's amazing how fast some of the old D.R.I. software runs, and with the 8080 to 68k emulator (COM2X), it is possible to run 8080 code too. Something like MBASIC.COM has very good performance even though it is running in an emulator!

Roger
 
I'm glad to have friends, I also made an SBC using the MC68SEC000 a while ago.
In order to make it a modern design, I connected the serial port via USB and implemented almost all of the logic using a LATTICE FPGA.

It's a small system with 1MB of SRAM and 1MB of Flash, but I designed everything from scratch, prepared an m68k gcc toolchain, and even got Lua running in REPL.

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Thank you! This is the first phase of my project and I hope to upgrade it in several phases.

I have only used 68k in an embedded environment and the hardware was not designed by me. Time has passed 25 years and I have just started working on my dream of the computer system designing and implementing everything from scratch by myself.

The two-line 7-segment LEDs provide real-time display of the address and data bus. However, there were restrictions on using an FPGA to drive these as they were, so I decided to use an ATMEGA32 to do the status LEDs, some buttons, and the responsibility of sending and receiving serial data, and then use an FPGA and SPI to send and receive the data.

I am not familiar with FPGAs, and this is the first time I have done a realistic design. I used it to learn how to implement basic logic circuits, decoders, and registers, how to control the 68k bus, and how to implement the SPI bus. I suppose I could have followed the wisdom of my predecessors and designed these circuits in the 74 series logic ICs, but I decided to use FPGAs from the beginning because I wanted to use the later series of 68k and develop them for display control and DRAM control. Besides, FPGAs give us the possibility to add functions later.
 
Here is another small 68000. Instead of FPGA, I found an inexpensive (<$10) CPLD development board based on EPM240 on eBay. I have designed a series of retro computer mezzanine boards (Z80, Z180, 6502, 68000) to plug on top of the EPM240 dev board. Pictures show the eBay's EPM240 dev board (blue board) and the 68SEC000 mezannine board. The mezzanine board has 1meg of RAM, SD card, I2C, and serial port. EPM240 dev board provides the bootstrap ROM, serial port, and glue logic. The design runs on 16. 7MHz, 3.3V.
Bill
 

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The SBC I built is available on GitHub: https://github.com/kekyo/Pixy

I plan to do a little upgraded design over a long span of time, but I plan to continue with the 68K series CPUs. So, do you guys consider PGA better than flat package?
I chose the flat package for the first version because:

* The 68000 which can run static at 20MHz, is only offered in a flat package.
* Assumption that since the FPGA is in a flat package either way, it would not be consistent in appearance if only the CPU was in PGA.
* 68SEC000-20 is inexpensive and easily available (for now).

Since 68EC020 seems to be relatively inexpensive, I intend to use the flat package when I proceed with the design for 68020, but I am a little unsure about what to do after 68030.
(I've already gotten flat packages up to 68EC040, but the 68060 is only available in PGA, so I'll have to switch even if I stick with the flat package.)
 
I think PGA is preferred because it is easier to assemble by hobbyists and can be removed for troubleshooting or salvaged for another project. 68020 and 68030 epoxy PGA are fairly inexpensive. 68040 and 68060 PGA are quite expensive, not too many hobbyist projects based on 68040 and 68060.
 
I think PGA is preferred because it is easier to assemble by hobbyists and can be removed for troubleshooting or salvaged for another project. 68020 and 68030 epoxy PGA are fairly inexpensive.
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That is certainly true. I understand the motivation to use PGA, which can be reused, especially since it is very expensive, especially for 68060.

As for design problems, I have the impression that wiring routing is difficult with PGA.
In my 68SEC000 project, I made it possible to use a flash ROM with a PLCC-PGA conversion socket, but I felt that the wiring in this part was difficult to do even with 4 layers (especially when the priority is to make use of the power plane).
On the other hand, the layout of components for efficient routing and FPGA pin assignments were very careful because the space between pins is narrow when using a flat package.

The FPGA pin assignments are not completely free (there are recommended pin assignments for some applications), so I had to consider that as a constraint, and I felt that this was not a problem that could be solved just by using FPGAs.

In fact, there was a time before I started this project when I wanted to somehow do it with DIPs and PGAs forms, but after doing a small-scale flat package implementation, I found that handling the stencil, handling the solder reflow oven, and hand solder rework techniques (see the YouTube demonstration of our predecessors), I found that it was not that difficult, so I switched to a policy of using flat packages across the board.

Video of hand solder correction:.


This is not the video I saw, but it looked almost identical to this one. It looks like you just squeeze out the flux in a syringe, apply it (very roughly), and trace it with a soldering iron.
This video seems to be an advertisement for this flux paste, but I think it should be fine as long as the flux is not of poor quality (mine is not this flux paste).
The points are:

* As shown in the video, apply as much as you think is too much.
* Trace quickly.
* Use less solder. If you use too much, it will accumulate at the end of the pins (even in this video, there is a small amount of solder on the remaining two pins.)
* The tip of the soldering iron should be flat.
 
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With current pcb design rules of 6 mil spacing and trace, I have not encountered problems routing to PGA. For an example, CB030 is a 68030 SBC in 100mmX100mm board that has 68030 PGA and CPLD in 100pin QFP, plus flash, duart, SIMM72. I’m able to route it in 2-layer and produced a number of boards. The latest CB030 pcb version is 4-layer mainly because DRAM is quite noisy and 2-layer pcb lacks solid ground return to reduce the ground noise.

I still solder SMT by hand one pin at a time, but I do it under microscope.
Bill
 
Thanks for the input. We are naïve about high clock operation due to lack of basic knowledge about noise and techniques/equipment to measure noise effects. This is something that was pointed out to me very often in the past when I worked for an embedded computer company (my main field of work is software design :)).

Therefore,

The latest CB030 pcb version is 4-layer mainly because DRAM is quite noisy and 2-layer pcb lacks solid ground return to reduce the ground noise.
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I really understand this. I'm thinking of using as wide a power plane as possible in the PCB 4 layers for design rehabilitation as well, since I will probably start working on a design that uses DRAM after this. With PGA, it is difficult to place the power plane under the footprint...
 
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