I/O issues on pdp8/l 1
IO doesn't seem to work.
M707 is bad, we know that.
M706 seems good but never gets past a skip instruction.
Possible problems:
Error in M111 D11. Swapped, no change.
Could be in the skip logic.
M111 B12 is a lot of logic here.
M160 in A13 has a lot of stuff feeding the skip flip flop.
Others feeding it are M113's and M115's.
Try switching A12 and A13. No change
Hm. Skips seem to be working as some skip on accumulator and skip on link instructions work.
M115 in C12 seems to be the NAND of IO Strobe, IO enable and Skip.
When I/O skip and I/O enable are both set, skip should be enabled.
IO_SKIP is A13K2 sourced from A33L1.
IO_ENABLE is "Big". A13J2, A35D1, B13M1,C12U2,D09J2, (ab02,3,4,5,6,7 bl2 is an input to the registers), B13M1,C12U2,D09J2
Swapped M160 at A13 again. No dice. K2 does not seem to get asserted but J2 does when running and it pulses rythmicly. K2 gets asserted only when system starts or continues.
J2 is I/O enable. K2 is I/O skip.
So we know IO/Enable is working, what about IO/Skip?
Comes from A33 L1
A33 L1 comes from three lines: Power skip, Reader skip, and TT skip.
H1,J1,K1 and F1 is some random input from outside.
All high except fir J1 low j1 is !tt int.
L1 is always high.
Hm. Something is wrong between A33/L1 and A13/K2
I see a possible wire wrap on A13 D1. ILLEGAL_REF. Oh that's nice.
Christ almighty I was getting sides 1 and 2 confused.
For the record:
Side 1 faces the front of the unit
Side 2 faces the rear.
The stuff on the bottom is accurate.
Side 2 has the +5 and ground lines.
If only one sided, it's side 2 by default (rare)
On A33, it's:
L1: I/O skip Output.
K1: PWR_SKIPg
H1: RDR_SKIP
J1: TT_SKIP
F1: to K2 of some socket.
Burned wire:
A28 B2 is the G785 main power system.
B34 B2 is the other end of the wire that burned.
Wire removed still nothing.
Note: Ran the input and output (echo program). It never sees that a keypress is done, so even the input skip is out. Can't be two bad lines, so it has to be something else here.
Is it possible that A13K2-A33L1 is broken? Maybe. Check it with a quick jumper. No, it's good with a 0 ohm resistance. So that's not it.
So what is the path for everything around here? And is it possible it's not the skip circuits but something else like the IO enable circuits?
Well, on the 707:
BH2 is I/O skip strobe
BJ2 is I/O skip
When program running and looping:
I/O skip strobe is low.
I/O skip is high
Address decoder is high.
Thus the not and would be a high output.
What if IOP1 is the problem? That's what they call the skip strobe.
IOP1 AB30 AU2 Paper tape reader
AB31 AR2 Paper tape punch
B15 H1
D02 F2-Our favorite inverter....
D31 H2--tty out
D32 D2--tty in
Edit: Oh great. After switching out two cards (C06/D06) the skip works but now it double skips.......
Actually it seems to triple skip. And that is weird, swapping C14 (the M113 that is supposed to clear the flip flop) doesn't change anything.
2/26/22:
More work. Could it be a bad wire on the IO_SKIP line? Will need to check.
Note pulled m706 still problem. Pulled A40 board (the one on the end that does power up) still problem. Pulled bus driver boards and load boards, still problem.
3/5/2022
Have a logic analyzer. Man this thing is useful. I can see that the raw Skip line is puling at a 36.676ms rate from the M707 meaning the card works (nice). I also put probes on the SKIP flip flop at M216 at B11, S1 and U1. Both report the same 36.676ms rate and are inverted meaning that the Slip flip flop, clearing circuitry, and all that garbage is working fine.
instruction 0 brief pulse low, high
instruction 1 brief pulse low, high
instruction 2 goes solid low
instruction 6 goes solid high (should be low, right?)
Moving down the line I did see something that might be odd: Checking the output of the M160 in A12 I saw that the output at R1 is ON 87% of the time. Which seems a bit off. Running the program in single steps shows a quick pulse when you press start (instruction 0), a quick pulse at 1, then a solid drop to LOW when instruction 2 is run, followed by a return to a solid high when instruction 6 is run (it should be 4 because 2 is the skip but it jumps way ahead). I haven't looked at Carry_insert (the output from the M113 at B13) but I wondered if the solid low during the skip is inserting as many carries as the computer can.
No, I tried switching A12 and A13 with known good parts earlier so it's not A12. Hm.
Might test it against my good pdp8/L to see what it does. Seems a bit odd, maybe one of the other lines is weird.
3/6/2022: Still, I think it's a problem with the SKIP ANDed with three inputs from IO. One is odd, _IO PC enable which comes from a NOT of IO Enable (M111 A35), TS4, and Pause (1) flip flop. Comes through M115 at C28.
However let's try replacing M111 A35. Tried swapping, still no dice.
3/8/22
Serious progress, then the computer went crazy again this morning. Here's the key notes:
First step was to look at the things that control adds from skips. That would be M160 at A12. Checking the output I saw that R1 was on almost all the time on the bad computer but was pulsing properly on the good computer. Focusing in I saw that SKIP(1) was fine, but INT_SKIP_ENABLE, IO_PC_ENABLE, and PC_ENABLE were all bad as follows:
So: On the bad pdp8L
Running:
t2 Red Goes low
U2 White Channel 1 Always high
T2 Green Channel 2 Always high.
V1: Always high
On the good pdp8/l
T2 Int Skip Enable Channel 0 high
U2 _IO PC ENABLE Channel 1 all sorts of pretty stuff.
V2 _PC ENABLE Channel 2 also different pretty stuff
V1 also pretty stuff.
!IO_PC_ENABLE comes from the following:
A08: In, U2
A14: In, U2 (of course)
C28: Out, D1
!PC_ENABLE
A08L In, T2
A14: in, V2 (duh)
B13: out, F1
C13: in, K1
The fact that both of them are down leads me to wonder if TS4 flip flop is being set properly.
Checked TS4 flip flop and it's clocking properly. So Time state 4 is working. I then went to see if !PC_ENABLE was receiving the TS4 signal at M113 B13 at which point the computer went insane again. Specifically:
MAJOR ERROR: I accidentally put the flip chips from the good pdp8L into A15 and B15. They were the ones that were supposed to be in A14 B14 but I had the bad pdp8l A14 and B14 up on risers.
Fuck.
Moving those two boards into the "good" pdp8/L and testing.
They work.
Moved into bad pdp8/L computer insane.
Moved boards back into original computers, I am taking a break, I am done with this for now.
Need to sit down and work on this. This happens, and I think it is due to wiring damage on the backplane.
Ok... Back.
Note when they go crazy, setting bits in the accumulator changes the increments in the MA when load address is toggled. This is something. More bits (11,10) causes bigger adds.
Start by checking location of all cards.
Right now I'm running the 8L with only one M220 to make it as simple as possible. It looks like examine and deposit work fine, and the computer will enter a run state but load address seems to be screwy in a consistient manner based on what is in the switch register at the time.
M220's are good, so it's related to the gating/switching logic.
03/09/2022
Well..... Figuring there was something insane with the count signal and knowing I have been swapping boards there I started at that point.
Pulling M160 at A12 isolated all the normal increment signals. Still happened.
Pulling the M113 at B13 stopped the count, so it was below that.
Pulling the M115 at A11 likewise did not increase the count, however plugging it back in fixed it.
Dirty connection or something at M115 A11.....
Back to the show
And look at that, now *everything* is working. Golly gee, I skip properly, increment properly, and the computer is doing everything right. Woot!
