Since we're talking about example applications for GALs...
Just for laughs here's a video I made talking about the basics of GALs and describing how I use them in a homebrew video card project I'm working on:
(Note that this video covers an intermediate stage in the development of this thing, the text below describes the state as of
next video about it.)
That project involves an Atmega8 MCU essentially emulating a 6545-style CRTC doing address and sync generation, and from there a pair of a GALs handle all the rest of the control and timing signal generation for the buffers, RAM/ROM chips, and output shift register. The first GAL, a 16v8, is mostly just a clock divider cutting the master clock generated by the crystal attached to the MCU into various user-selectable pixel clocks, and the second one, a 22v10, does all the dirty work counting out groups of six or eight bits (character cells can be six or eight pixels wide), controlling the chip enable/read lines for the memory chips and the buffers that alternate between the "video scan" memory fetch and the "character generation" fetch. (These buffers are not in the GAL-specific video, they were added in the next one.) It also generates a PHI clock to drive a 6502 so any memory requests from the 6502 will come on the opposite phase as requests from the video system, so it can do "no interference" sharing of memory between a CPU and video like an old 80's home computer (Apple II/Commodore 64/whatever) did.
(There's actually a third GAL in the next video where the CPU shows up, but all it does is handle the memory map selection for the 6502 tacked off on the side, it's not directly involved with video generation.)
This where GALs truly shine, making mixed-logic state machines that otherwise would require a ton of discrete parts. Both GALs have three bit counters embedded in them with logic to reset them at specific counts or generate fractional divisions. For instance, my clock divider circuit can generate an 8mhz clock from a 12mhz master clock by counting through 6 full cycles of the input clock and changing the state of the 8mhz pin four times by alternating between states that are based on both the counter register contents and the phase of the input clock signal. (The resulting output does have a 33/66% duty cycle instead of 50-50, but that's fine for this). The main control GAL also has a one-shot flip-flop embedded in it I'm kind of proud of that lets the MCU semi-asynchronously tell the GAL to actually start spitting out characters during the active period of a line and when to stop. This means the code that does address generation *only* has to count addresses in a loop, it doesn't have to twiddle a control line for every character. Certainly you could implement similar control logic with discrete chips, but... I haven't sat down and tried to actually translate everything into available TTL packages but I would guess it would be in the ballpark of at least a dozen chips, probably more.
Anyway. FWIW, I just sat down with the text editor and tried to noddle out if all the moving parts for Myke's schematic as-is would fit in a 22v10 and I think we're several pins short of being able to replace *everything*. The fact that there needs to be six output CS lines, two external buffer select lines, and swallowing up the 74LS74 requires another two registered/output pins sucks up all the outputs of a 22v10. At the very least I think there would need to be one more select output for bus buffer control. (And we're also getting really tight on inputs; there's 8 bus address lines, two data lines if the 74LS74 is internalized, IORQ, WRITE, and probably READ unless the buffer structure was modified.)
Easiest fix is probably keeping one of the 74LS138s to decode the chip select for the 6 separate RAM chips? I think that'd free up just enough to fit everything else internal. Maybe if you were lucky there would be just enough to add one more registered I/O pin and data input to give you 18 bit addressing instead of 17 bit so you could use the GAL unchanged to drive a 512K RAMdisk with single a modern SRAM on it instead.