Hello Everyone,
I'm currently in the process of troubleshooting my IBM PC XT/286 5162 which doesn't boot or beep with the stock ROMs.
When trying with SuperSoft diag BIOS, sometimes I get no beep at all, sometimes it will start beeping completely erratically (like there are random resets every 0.1sec to 1sec) and finally hangs (with a continuous beep if it was beeping while hanging)
After hours of probing with a scope, I found something really interesting using this procedure : https://www.minuszerodegrees.net/5162/diag/IBM 5162 - Ground IO CH RDY.htm
If I ground I/O CH RDY pin on an ISA slot, I still get CPU activity after the startup reset, sometimes for a few seconds, sometimes it never stops.
If I probe the READY signal when I have the CPU in this weird activity state, I can see a square signal coming from the 82284 just because the CPU tries to access and write to RAM (and so will enable SRDY signal through the 82288)
I'm really at a loss here because if I understand the 80286 reset sequence correctly, with I/O CH RDY grounded, it should simply tries to access the ROM, so it would push 0xFFFF0 on its address lines and S0,S1,M/IO,COD/INTA signals should be 1,0,0,1 respectively to signal at the 82288 an I/O read... and so the READY signal should always stay high with the CPU indefinitely waiting with no activity.
I tried with another 80286 (a CG 80286-8 C from a working IBM 5170) with same results.
Does anyone know exactly how should look like a reset sequence of a 80286 ? Because I'm getting activity on the S1 line only 3.3µs after the falling edge of the reset signal and this seems really strange to me...
Thank you!
I'm currently in the process of troubleshooting my IBM PC XT/286 5162 which doesn't boot or beep with the stock ROMs.
When trying with SuperSoft diag BIOS, sometimes I get no beep at all, sometimes it will start beeping completely erratically (like there are random resets every 0.1sec to 1sec) and finally hangs (with a continuous beep if it was beeping while hanging)
After hours of probing with a scope, I found something really interesting using this procedure : https://www.minuszerodegrees.net/5162/diag/IBM 5162 - Ground IO CH RDY.htm
If I ground I/O CH RDY pin on an ISA slot, I still get CPU activity after the startup reset, sometimes for a few seconds, sometimes it never stops.
If I probe the READY signal when I have the CPU in this weird activity state, I can see a square signal coming from the 82284 just because the CPU tries to access and write to RAM (and so will enable SRDY signal through the 82288)
I'm really at a loss here because if I understand the 80286 reset sequence correctly, with I/O CH RDY grounded, it should simply tries to access the ROM, so it would push 0xFFFF0 on its address lines and S0,S1,M/IO,COD/INTA signals should be 1,0,0,1 respectively to signal at the 82288 an I/O read... and so the READY signal should always stay high with the CPU indefinitely waiting with no activity.
I tried with another 80286 (a CG 80286-8 C from a working IBM 5170) with same results.
Does anyone know exactly how should look like a reset sequence of a 80286 ? Because I'm getting activity on the S1 line only 3.3µs after the falling edge of the reset signal and this seems really strange to me...
Thank you!