eeguru
Veteran Member
In the near future I'm working on a hobby hardware design that interfaces either a Lattice MachXO2 or XP FPGA to an ISA card and bus. The issue of what to do with voltage level conversion came up first and furious as I still haven't found a best guess solution.
(as I understand things.. still learning)
ISA is complicated. Since it was developed by IBM and everyone cloned it, there never was a clear electrical standard in the old PC days. Every clone manufacturer did things best guess and as a result there are tens of thousands of hardware designs with differing bus impedance, typical I/O levels (anywhere from 4V to 5V for later CMOS), and resulting slew rates, overshoots, and sag. The Lattice parts I'm looking at (as well as some from Altera and Xilinx) have internal clamping diodes intended for 5V PCI compliance. However thay all seem to have a low max current limit (~10mA) requiring a series resistor to restrict it. The typical value calculation, depending on how much overshoot protection is needed, works out to ~300 ohms +/- 30. I'm worried that using a resistance that high might cause an I/O voltage sag on some motherboards during ringing, depending on the effective matching bus impedance; resulting in the voltage read on the other end of the bus becoming marginal for TTL positive logic detection (2.4V) on some devices manufactured back in the 'golden days'. It really depends on the effective bus impedance of the motherboard being plugged into, but this card - if I'm tenacious enough to see it through - might be useful to a lot of other vintage hobbests and their systems; not just mine. So I have to plan for worst case.
There are 4 ways I can fix this and I'm not sure which is the best one:
(feel free to stop me and call me an over-thinking idiot at this point)
A) Rely on the internal clamps and use series resistors to limit the current assuming a max .5 overshoot. This is certainly the cheapest but I have the least confidence in it. Cost is a big concern. Even though the final design will basically be a SoC, I may need to switch to a BGA package for the FPGA depending on I/O requirements - which is already threatening to blow my cost budget to hell.
B) Use external clamp diodes with a much higher current limit eliminating the need for such a high and problematic series resistance. This may be the most costly component-wise since adding enough diodes for 50 16-bit ISA input or input/output lines in packages that only gang up to 4-6 really piles up $$ in small quantities.
C) Use a FET based logic level converter similar to CBTD16211DGG. This is a new part from Phillips that does the same job as option B and is really suprisingly cheap. However it does add 2 significant ICs and likely more costly than A depending on where and how the boards are stuffed (either a house for BGA + common tape or 100% me if QFP/SOIC/SSOPs).
D - Hybrid of A & B/C) Use A for lines that are strictly inputs (addresses, strobes, dma acks, etc) and use either option B or C for the data lines. Leave output only lines (IRQs, DRQs, etc) push-pull and directly connected.
I'm also unsure if I should add any noise suppression resistors to any of the signals. They're pretty typical when you have high frequency routed all over the board, but the only thing high frequency on this design is a single DDR SDRAM. I could probably skip them with careful routing and placement.
Just was wonding if there's anyone here with $.02 to spare.
(as I understand things.. still learning)
ISA is complicated. Since it was developed by IBM and everyone cloned it, there never was a clear electrical standard in the old PC days. Every clone manufacturer did things best guess and as a result there are tens of thousands of hardware designs with differing bus impedance, typical I/O levels (anywhere from 4V to 5V for later CMOS), and resulting slew rates, overshoots, and sag. The Lattice parts I'm looking at (as well as some from Altera and Xilinx) have internal clamping diodes intended for 5V PCI compliance. However thay all seem to have a low max current limit (~10mA) requiring a series resistor to restrict it. The typical value calculation, depending on how much overshoot protection is needed, works out to ~300 ohms +/- 30. I'm worried that using a resistance that high might cause an I/O voltage sag on some motherboards during ringing, depending on the effective matching bus impedance; resulting in the voltage read on the other end of the bus becoming marginal for TTL positive logic detection (2.4V) on some devices manufactured back in the 'golden days'. It really depends on the effective bus impedance of the motherboard being plugged into, but this card - if I'm tenacious enough to see it through - might be useful to a lot of other vintage hobbests and their systems; not just mine. So I have to plan for worst case.
There are 4 ways I can fix this and I'm not sure which is the best one:
(feel free to stop me and call me an over-thinking idiot at this point)
A) Rely on the internal clamps and use series resistors to limit the current assuming a max .5 overshoot. This is certainly the cheapest but I have the least confidence in it. Cost is a big concern. Even though the final design will basically be a SoC, I may need to switch to a BGA package for the FPGA depending on I/O requirements - which is already threatening to blow my cost budget to hell.
B) Use external clamp diodes with a much higher current limit eliminating the need for such a high and problematic series resistance. This may be the most costly component-wise since adding enough diodes for 50 16-bit ISA input or input/output lines in packages that only gang up to 4-6 really piles up $$ in small quantities.
C) Use a FET based logic level converter similar to CBTD16211DGG. This is a new part from Phillips that does the same job as option B and is really suprisingly cheap. However it does add 2 significant ICs and likely more costly than A depending on where and how the boards are stuffed (either a house for BGA + common tape or 100% me if QFP/SOIC/SSOPs).
D - Hybrid of A & B/C) Use A for lines that are strictly inputs (addresses, strobes, dma acks, etc) and use either option B or C for the data lines. Leave output only lines (IRQs, DRQs, etc) push-pull and directly connected.
I'm also unsure if I should add any noise suppression resistors to any of the signals. They're pretty typical when you have high frequency routed all over the board, but the only thing high frequency on this design is a single DDR SDRAM. I could probably skip them with careful routing and placement.
Just was wonding if there's anyone here with $.02 to spare.
Last edited:
