I have made some calculations. Starting from the 8MHz clock I found that going through C9 QB, QC, QD and C8, that C8 pin 2 should go low about 45ns after the falling edge of the 8MHz clock (C9 pin 1). On the other hand, going through D8 and C8 again, the reset pulse should cause C8 pin 2 go high again 25ns after the rising edge of the 8MHz clock.
Between falling and rising edge of an 8MHz clock are 63ns, so the pulse should go from 45ns to 63ns+25ns=88ns (counted from the falling edge of the clock). I.e. the pulse on C8 pin 2 has a pulse width of 88ns-45ns=43ns (approximately). But that corresponds well with the signals as taken from the working PET and is fine within all TTL / input specs.
Now, on the broken PET, if the C9 counter only has a delay of 5ns more per counting step, the pulse would loose another 15ns, resulting in a pulse of 30ns width only.
This picture
http://web.me.com/lord_philip/other_computers/20012.html#71 actually shows that the pulse is only about 20ns, compared to the 40ns as per spec.
We can actually also see an indication for this in
http://web.me.com/lord_philip/other_computers/20012.html#78 . The trigger is the reset signal from D8 going into C8 pin 13. The start of that signal is triggered via the rising 8MHz clock, so we have a reference to that clock. Now the 8MHz clock is divided and we see the result in the second signal on that picture. And we see that the counted clock is about 10-15ns later in the broken PET than it is in the working PET.
Assumptions made: for C9, D8 each step is a standard LS delay of 10ns, my data book says 15ns for the 'LS107 at C8.
Edit: My calculations:
http://www.flickr.com/photos/afachat/5772084301/in/photostream/lightbox/
