Another PET 2001 motherboard needs your help...

[dave_m]

Covering my bases, here is my kludge fix just in case we never get to the bottom of the real issue.
I've had the board up and running Android Nim for 3 hours now with no issues seen with this cap in place.

http://web.me.com/lord_philip/other_computers/20012.html#84

Dave,yes I did the voltage reading with my digital multimeter. I haven't had time this evening to do any scope test as I've had my hands full with my 2 year old son!!!!

Phil,
Well that will make for a neat looking mod in case it is needed, but we will get to the bottom of this soon.

Looking at the schematic again, with C8-3 lifted, the only way the output can be a steady low, would be if the drop of the clock to the C8 flip-flop came AFTER the rise of the 8 MHz clock. In that case, the reset beats the clock to C8 and keeps the Q (C8-3) low.

For that to happen, it would mean the delay in the ripple counter must be greater than 63 nS!!

When you get a chance, we need to do the delay measurement that André and Mike are asking for...

EDIT: I looked up the spec for the LS93, typical for the delay is 34 nS as we thought, but the max delay is spec'd at a whooping 51 nS. Your counter may be six sigma slow at > 63 nS!!

 

[Nama]

Phil,
When you get a chance, we need to do the delay measurement that André and Mike are asking for...

Again, can you kindly describe how i should go about this?

Cheers

 

[dave_m]

Again, can you kindly describe how i should go about this?

Cheers

Phil,
We are looking for a 'race' condition between the rising edge of E2-6 (8 MHz clock) and the drop of the 1 MHz clock as measured at C8-12.

If it turns out to be more convenient, the 8 MHz can be measured at D8-9.

You can temporarily tack solder short wires to those pins to make it easier to clip on the scope probes, if that makes it easier.

Channel one should be the 1 MHz clock and set the trigger for the positive edge of that pulse. The time base should be set for around 0.2 uS per division.

For proper operation, the 1 MHz clock should drop a good 30 nS before the rise of the 8 MHz. If they are happening very close to the same time, there is a race condition which is very bad.

It would be best to use a delayed sweep setup for this measurement, but let's not worry about that for now.

 

[MikeS]

...When you get a chance, we need to do the delay measurement that André and Mike are asking for...

Me??? Nah, I doan' need no steenkin' delay measurement; just replace that @$^% 74LS93 like I suggested way back when, so I can either brag "I told you so!" or quietly slink away muttering "never mind..." ;-)

Sorry, busy with 'real' work so haven't been keeping up with latest developments but will try to get caught up.

 

[fachat]

Yes, same for me, busy with work. A lot has been discussed here. But I think as a next step you should indeed do the delay measuring. I.e. on one channel, use C8 pin 3, and use it as a trigger, on the other channel measure the 8MHz clock, e.g. at D8 pin 9.

Compare the pictures from both the broken and the working PET.

André

 

[dave_m]

Me??? Nah, I doan' need no steenkin' delay measurement; just replace that @$^% 74LS93 like I suggested way back when, so I can either brag "I told you so!" or quietly slink away muttering "never mind..." ;-)

Hey, I feel bad enough about realizing that you and André had the right answer a week ago until I made Phil try all these hair-brained schemes with capacitors, etc.

Anyway, how did I know you were an expert on the 74LS93? Of course, at Rockwell we would have died first before using a ripple counter in a master clock circuit!

But I know you really agree we should take the measurement first before replacing parts...

Sorry, busy with 'real' work so haven't been keeping up with latest developments but will try to get caught up.

Hey, since when do we let real life interfere with fixing a PET?

Look at Phil - his young son was crying for Daddy for an hour before Phil stopped his work!

 

[dave_m]

A lot has been discussed here. But I think as a next step you should indeed do the delay measuring.

André,
Yes I agree.

And your excellent timing analysis may be the key breakthrough in fixing this problem.
-Dave

 

[tezza]

Boy,

Just like their warm-blooded furry counterparts these PETs need a lot of care, attention and grooming. I'm almost afraid to fire mine up again!

Most of this stuff is over my head, but it's great to see a deep and difficult issue being diganosed by the community this way.

Tez

 

[dave_m]

Most of this stuff is over my head, but it's great to see a deep and difficult issue being diganosed by the community this way.

Tez,
You did a great job with your PET.

This problem Phil is working on is just plain nasty. I think it is boiling down to an out of spec counter in a countdown chain, causing a timing race condition at a flip-flop that creates the clock that increments the video RAM address used to refresh the screen. The only symptoms seem to be that displayed characters are displaced a few positions on the screen.
-Dave

 

[Nama]

I'm almost afraid to fire mine up again!

Tez

Terry, I can hear your PET calling your name. "Terry, Terry, play with me, love me, fire me up...please"

 

[tezza]

Terry, I can hear your PET calling your name. "Terry, Terry, play with me, love me, fire me up...please"

Hehehe.

For the record I did have the PET out the other day for photos by some visitors. It still goes, and seems to be a well behaved and happy little beast (whew!).

Tez

 

[tezza]

Tez,
You did a great job with your PET.

Well in truth Philip Avery and Andres (and you guys) did way more than me. I learnt some things though.

This problem Phil is working on is just plain nasty. I think it is boiling down to an out of spec counter in a countdown chain, causing a timing race condition at a flip-flop that creates the clock that increments the video RAM address used to refresh the screen.

Yes. Now if only I could understand that sentence

Just kidding, remarkably I can kind of follow what you are saying Dave. That condition is REAL nasty. Just goes to show that some things can be incredibly complex to track down and needs a really deep understanding of just how these things work plus some tricky diagnostic techniques. If you guys crack this one, you can all be very proud of yourselves.

Tez

 

[Nama]

Ok I've posted some images. I got a little confused at one point, so I'm hoping the images are still valid:

Broken board: C8-3 (trigger) and D8-9
http://web.me.com/lord_philip/other_computers/20012.html#85
and
http://web.me.com/lord_philip/other_computers/20012.html#87

Working board: C8-3 (trigger) and D8-9
http://web.me.com/lord_philip/other_computers/20012.html#86
and
http://web.me.com/lord_philip/other_computers/20012.html#88

also
Broken Board: C8-12 (trigger) and E2-6
http://web.me.com/lord_philip/other_computers/20012.html#89
and
http://web.me.com/lord_philip/other_computers/20012.html#91

Working Board: C8-12 (trigger) and E2-6
http://web.me.com/lord_philip/other_computers/20012.html#90
and
http://web.me.com/lord_philip/other_computers/20012.html#92

Phew!

 

[dave_m]

Well in truth Philip Avery and Andres (and you guys) did way more than me. I learnt some things though.

Yes, I remember Philip Avery helped a lot on your early projects and loaned you some test equipment. How is he doing?

Just goes to show that some things can be incredibly complex to track down and needs a really deep understanding of just how these things work plus some tricky diagnostic techniques. If you guys crack this one, you can all be very proud of yourselves.

Yes, in the old days, the boards had a lot of what is called small scale logic (small chips) on the board which made troubleshooting a little tricky and a lot of fun.

All the logic we are exploring in this problem would later be embedded in a big 40 pin CRT controller chip. If it goes bad, the only solution is to replace it without need for a lot of thought. Easier, but a lot less fun.

Even worse, the modern electronics/PCs of today are usually complete throwaways when they fail. Everything is in a few big chips that are too difficult and costly to replace as no amateur can handle a 300 pin surface mount part. You usually can't even probe them without shorting things out.

So those of us that love troubleshooting have to keep an ancient computer around.

 

[Nama]

I've done a quick composite of two of the images, and have tried my best in a short time to align everything:

http://web.me.com/lord_philip/other_computers/20012.html#93

This is for the C8-3 (trigger) and D8-9 reading. I'm not sure of the time scale here as this was zoomed in using the variable dial on the scope, but it shows a big difference in timing for sure.

 

[MikeS]

I've done a quick composite of two of the images, and have tried my best in a short time to align everything:

http://web.me.com/lord_philip/other_computers/20012.html#93

How are you doing those lovely coloured composite images?

 

[dave_m]

This is for the C8-3 (trigger) and D8-9 reading. I'm not sure of the time scale here as this was zoomed in using the variable dial on the scope, but it shows a big difference in timing for sure.

Phil,
You put your finger on the problem. While there seems to be no issue with the LS93 counter, it seems obvious to me that the C8-3 output of the flip-flop is starting to reset BEFORE the rise of the 8 MHz clock. This can not be. The problem must be around the premature reset of the flip flop. Either the C8 flip flop is bad (and one has been replaced already) or the D8 NAND gate is bad.

The next step is to probe the NAND gate, pin 8 vs pin 9 and 10.

The fun never stops!

 

[Nama]

How are you doing those lovely coloured composite images?

Magic!

...or the next best thing, Photoshop.

 

[Nama]

The next step is to probe the NAND gate, pin 8 vs pin 9 and 10.

The fun never stops!

So D8-8 is the trigger for D8-9 and D8-10, correct?

 

[dave_m]

Yes, that should be OK. D8-8 is the reset signal and will be a skinny negative-going pulse that occurs every 1 uS. D8-10 is connected to C8-3 so you can use that point if you already have a probe on it. Use the 0.2 uS/DIV sweep rate.