Learning VHDL Programming language - Altera CPLD programming

[Gerry_MAN]

Hey Folks, :happy5:

Before I begin:
I have started up this Yahoo Group devoted to VHDL programming.

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http://tech.groups.yahoo.com/group/VHDL_CODE/
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I've have posted here in the past regarding my Vintage "Altera Master Programming Unit" used for Programming Altera CPLD chips
and FPGAs.

Now, I also wanted to mention the ongoing learning of the Programming language for implementing Digital Logic into CPLDs and FPGAs;
that being the VHDL Digital Logic programming language. Not all of you may be aware of this Language.

This VHDL code can be used to design your Digital Logic and then be programed into your CPLD. This is an equivalent form of programming, just like the Digital schematic form of programming a CPLD.
Most students are introduced to this Graphical form of programming & design, which uses Gates and or various digital components within a Graphically based Logic design software.

Programs like Altera MAX+Plus II, Altera Quartus II and Active HDL. There is also more sophisticated Programs like HDL Designer by Mentor Graphics.
These all use a standard Graphical programming form that allow the user to design using a Digital schematic. Now, not all student realize that you can also use these programs I mentioned above,
to implement a design using this Programming language called "VHDL". This is actually equivalent to their Digital schematic.
In Actuality, the software will take the Graphical Schematic and convert it automatically into VHDL prior to programing the CPLD or FPGA.

I know many Students and beginners have been looking high and low for simple descriptions on how the language works, but all they find are extremely complex
programming manuals. This can be very confusing and frustrating....especially for beginners.

So I decided to start up a Yahoo Group forum, that is devoted entirely to VHDL programming.

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http://tech.groups.yahoo.com/group/VHDL_CODE/
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So hopefully people will join as time goes on, and we can try to help those seeking to learn this great and wonderful language.

Kind Regards,
Gerry O'Brien
http://www.digital-circuitry.com

 

[eeguru]

Verilog can often be an easier starter language for those coming from a more software background. It's syntax is lines up better with many low level software languages. Ultimately any FPGA programmer is very familiar with both from necessity. And of course all the same concerns and pitfalls apply to both - especially someone coming from software.

I don't mean to hijack your thread, but it's certainly worth mentioning as it has larger traction in corporate North America.

 

[Chuck(G)]

For vintage CPLDs, I prefer Xilinx to Altera--more often, one can get more done with fewer macrocells. And I use Verilog on these crufty beggars.

I have to admit confusion, however. What does this have to do with vintage computers?

I'd expect most students would skip the CPLD stage and go directly to FPGA if they wanted to implement old CPU architectures. If you're exploring the field of programmable logic, FPGA devkits certainly have more "bang for the buck" than do CPLD ones.

I think you could clear this up with a bit more explanation of your intended purpose here as it applies to vintage computers.

Speaking personally, I get a sick feeling when I see a vintage board with a custom gate array or registered PAL/PLA on it, knowing that I'll never figure out what's under the epoxy. CPLDs will pose a similar problem to future vintage collectors--20 years down the road, they're unobtainable and the programming is impossible to figure out. More eTrash.

Thanks!

 

[eeguru]

The lines are blurring. Three things traditionally differentiated CPLDs from FPGAs. First, the latter had a more complex and configurable cell architecture. Usually with the combinatorial and registered components very loosely coupled within a larger unit (SLICE, CLB, PFU, etc). Where as a CPLD had a less complex macro cell with a single multi-input AND or OR, sometimes an additional XOR, and a direct coupled FF. Now the larger CPLDs are adopting the same cell architecture as their big FPGA brothers. The second was capacity range. Now, from many vendors, you can get the largest part branded CPLD in a capacity greater than the smallest FPGA part variant. The last has been CPLDs typically have ROM/Flash backed net configuration where FPGAs have traditionally loaded theri RAM from off-board. That's also changing as a lot of FPGAs now are instant on.

To answer Chuck's point, PLDs are often either the easiest or only way of addressing interfacing problems for machines made 30 years ago.

 

[Chuck(G)]

To answer Chuck's point, PLDs are often either the easiest or only way of addressing interfacing problems for machines made 30 years ago.

I'd say only "easiest". Unfortunately, from an archival point of view, they're just a black box 20 years down the road. I have no quarrel with programmable logic per se, heck, I use it myself, but how popular as a collector's item would have the PC been if it was implemented in FPGA with the security fuses blown--and no extant documentation?