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PC and PC/XT ISA REFRESH Line

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pearce_jj

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I found this:

"The ISA adapter card can generate refresh cycles without relinquishing control of the bus by asserting REFRESH. MRDC can be then monitored to determine when the refresh cycle ends."

Does this work in a PC or XT? In the original tech ref the line is labelled DACK0 although the description isn't clear, "These lines are used to acknowledge DMA requests (DRQ1-DRQ3) and to refresh system dynamic memory (DACK0)."

Any experience with this? Can an ISA card in an XT force a memory refresh during a block-mode DMA transfer by asserting REFRESH?
 
The PC and XT uses the actual DMA Channel 0 to refresh memory, while The AT has a memory-refresher based on discrete logic components. To keep compability with PC/XT cards and to make DMA Channel 0 available for other use in the AT, the DACK0 pin was changed to REFRESH and the actual DACK0 signal was moved to the 16-bit portion of the ISA connector.

So while it may be named DACK0 in PC and XT class machines, it does represent memory refreshes.
 
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Don't know where you found it, but DACK0/ (B19) is driven by an always-enabled LS244 output on the 5150/5160, so there's not a thing you can do with it other than read it.
 
Chuck(G) said:
Don't know where you found it, but DACK0/ (B19) is driven by an always-enabled LS244 output on the 5150/5160, so there's not a thing you can do with it other than read it.
Click to expand...

According to the IBM PC and XT techrefs, the input of that LS244 output is connected directly to /DACK0 of the 8237.

As mentioned, the only use for this signal would be to check if a memory refresh is curently being executed.
 
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per said:
According to the IBM PC and XT techrefs, the input of that LS244 output is connected directly to /DACK0 of the 8237.

As mentioned, the only use for this signal would be to check if a memory refresh is curently being executed.
Click to expand...

Exactly--it's a status pin only.
 
Many thanks for the replies. The source was the ISA System Architecture, 3rd ed although the chapter in question isn't in the free version. So I guess the use to generate refresh arrived later.

In that case it looks to me that DMA block-mode transfers can only be about 16 bytes each, to avoid suppressing RAM refresh on an XT?
 
I haven't checked, but isn't XT refresh RAS-only? As long as you're transferring at least 256 bytes at a toss without adding wait states, it wouldn't seem to make much difference.
 
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