4164/41256 interfacing

[cr1901]

I'd never suggest doing this (or try this myself) for a hobbyist project, but... how would one correctly interface the 4164/41256 ICs to a processor which outputs the all address bits simultaneously? The way these ICs are designed, the bit locations are multiplexed into rows and columns of bits to reduce the number of wire connections required (a standard technique, if I remember correctly), and a row/column strobe differentiates whether the input address is for the desired column or row. Since a data bit in the 4164/41256 ICs therefore cannot be accessed in a single system or memory* bus clock cycle, where is the data stored in between the row/column strobe, if a processor such as the 8088 outputs the entire address is one cycle- a buffer IC? What additional glue logic is required to properly interface to these RAM chips?

*In these old PCs, the system and memory bus run at the same speed, inserting wait states as necessary, correct?

 

[Chuck(G)]

I'm not looking at the 5150/5160 schematics, but I seem to remember that they used a delay line for the RAS-CAS interval. I've also seen manufacturers do it on the cheap with a few sections of an inverter strung together to get the proper timing. LSI DRAM controllers just use a fast clock divided down to get the right timings.

There are DRAMs that don't multiplex address lines--the venerable 4Kx1 TMS4096 is one such example.

 

[cr1901]

I'm not looking at the 5150/5160 schematics, but I seem to remember that they used a delay line for the RAS-CAS interval.

If I had a shred of common sense, I would've looked up the schematics before asking... oops. Also delay line... hooray for DSP coming back to haunt me :D! That makes sense now that I think about it, without having consulted the schematics. I imagine that the LSBs of the address bus and the RAS assert signal are sent into a latch which is connects to the 41xx inputs, and the MSBs of the address bus, the CAS assert signal, and the bit to be stored (assuming write) are sent through the delay line IC, and output to the same latch? Or something like that...

There are DRAMs that don't multiplex address lines--the venerable 4Kx1 TMS4096 is one such example.

I have learned something today .

Well, if a

 

[Chuck(G)]

Okay, let's take the events one by one for clarification. You don't need a delay line, but you want things to run as fast as possible, so you don't want to waste clock cycles--and that's where a delay line comes in. Recall that the 4164 is an asynchonous DRAM chip, which means that things don't happen in lockstep with the CPU clock.

If you're using a CPU like the 8088 with multiplexed data and address lines, you have to latch the address (one of the things that makes the 8088 slower than it really needs to be--but such are the limitations of a 40 pin DIP).

So, you first present the row address on the DRAM address lines, then pulse RAS/ and keep it low for a minimum of somewhere around 150 nsec for the 4164--which essentially forms an "envelope" around the rest of the operation. You also decide if you're reading or writing and set the WE/ pin whichever way is applicable. If you're writing, you also present the data on the data line at this time. About 30 nsec or so (RAS-to-CAS precharge time) after you've presented RAS/, you put the column address on the address pins and drop CAS/--this is where the delay line comes in--30 nsec is a very short time in the world of the 8088 and because you're likely using a mux to select either row or colum select, you've got to have a little lead time before asserting CAS to allow the address to stabilize through the mux--this can be handled very neatly by a tap on the delay line, assuring that the column address will be where it needs to be when it needs to be.

At the end of the 150-or-so nsec. RAS/ cycle, you de-assert RAS, collect your data if you were reading (OE/ pin) and then de-assert /CAS and you're good to go.

That's the simple picture. The 4164 has several other modes, such as "early write", "read-modify-write" and "page mode" where several CAS cycles can be performed under a single RAS cycle.

You could dispense with the delay line by running a faster clock and using a shift register or counter or decoder, but in 1981, that had design issues of its own.

Take a look at Tim Olmstead's article from 16+ years ago for a step-by-step using the Z80 CPU.

 

[sergey]

That's why in hobbyist projects like Xi 8088 or N8VEM SBC we now use SRAM It is much easier to interface with... no address multiplexing, no refresh logic, and luckily SRAM parts are still being manufactured (which is not the case with low capacity DRAMs).

BTW in some case we are doing the opposite thing - adapting the circuit to use SRAM instead of DRAM, which is done by adding some address latches...

 

[Chuck(G)]

Well, bits-for-the-buck, DRAM still tops the list. There have even been a few enterprising souls who have hooked the likes of an AVR MCU to a DRAM SIMM.